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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
NASA NTRS1993

Method for producing a hybridization of detector array and integrated circuit for readout

A process is explained for fabricating a detector array in a layer of semiconductor material on one substrate and an integrated readout circuit in a layer of semiconductor material on a separate substrate in order to select semiconductor material for optimum performance of each structure, such as GaAs for the detector array and Si for the integrated readout circuit. The detector array layer is lifted off its substrate, laminated on the metallized surface on the integrated surface, etched with reticulating channels to the surface of the integrated circuit, and provided with interconnections between the detector array pixels and the integrated readout circuit through the channels. The adhesive material for the lamination is selected to be chemically stable to provide electrical and thermal insulation and to provide stress release between the two structures fabricated in semiconductor materials that may have different coefficients of thermal expansion.

Fossum, Eric R.↗
NASA NTRS1975

Contact-eutectic-lens fabrication technique

Method enables use of crystal or semiconductor materials with selective spectral-response characteristics (ultraviolet, visible, or infrared wavelengths) in fabrication of contact lenses, reading glasses, and photographic processing equipment.

Allen, F. G.↗
NASA NTRS1980

Epitaxial and polycrystalline GaAs solar cells using OM-CVD techniques

GaAs epitaxial films were grown by chemical vapor deposition using organo-metallic sources (OM-CVD) on single crystal and polycrystalline bulk GaAs, as well as on bulk polycrystalline and recrystallized thin-film Ge substrates. Details of Antireflecting Metal-Oxide-Semiconductor (AMOS) solar cells fabricated on GaAs films grown on bulk polycrystalline Ge and recrystallized Ge thin-film substrates will be discussed, as well as preliminary photovoltaic results obtained for n(+)/p homojunction structures.

Yeh, Y. C. M.↗
NASA NTRS1990

Chemical nature of silicon nitride-indium phosphide interface and rapid thermal annealing for InP MISFETs

A rapid thermal annealing (RTA) process in pure N2 or pure H2 was developed for ion-implanted and encapsulated indium phosphide compound semiconductors, and the chemical nature at the silicon nitride-InP interface before and after RTA was examined using XPS. Results obtained from SIMS on the atomic concentration profiles of the implanted silicon in InP before and after RTA are presented, together with electrical characteristics of the annealed implants. Using the RTA process developed, InP metal-insulator semiconductor FETs (MISFETS) were fabricated. The MISFETS prepared had threshold voltages of +1 V, transconductance of 27 mS/mm, peak channel mobility of 1200 sq cm/V per sec, and drain current drift of only 7 percent.

Biedenbender, M. D.↗
NASA NTRS2002

An IDEA of What's in the Air

The Automatic Particle Fallout Monitor (APFM) is an automated instrument that assesses real-time particle contamination levels in a facility by directly imaging, sizing, and counting contamination particles. It allows personnel to respond to particle contamination before it becomes a major problem. For NASA, the APFM improves the ability to mitigate, avoid, and explain mission-compromising incidents of contamination occurring during payload processing, launch vehicle ground processing, and potentially, during flight operations. Commercial applications are in semiconductor processing and electronics fabrication, as well as aerospace, aeronautical, and medical industries. The product could also be used to measure the air quality of hotels, apartment complexes, and corporate buildings. IDEA sold and delivered its first four units to the United Space Alliance for the Space Shuttle Program at Kennedy. NASA used the APFM in the Kennedy Space Station Processing Facility to monitor contamination levels during the assembly of International Space Station components.

Source record↗
NASA NTRS1996

Porous silicon carbide (SIC) semiconductor device

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

Shor, Joseph S.↗
NASA NTRS1981

Chemical composition of the SiO2/InSb interface as determined by X-ray photoelectron spectroscopy

In connection with the relatively poor insulating characteristics of the native oxides of most III-V compound semiconductors, there has been interest in the development of deposited dielectric layers for surface passivation and MOS device fabrication on III-V compound semiconductor substrates. The chemical system of SiO2 deposited on single-crystal InSb substrates has been proposed for the fabrication of IR CCD. The considered investigation is concerned with a detailed examination of the chemical nature of the interactions between deposited and native oxides using X-ray photoelectron spectroscopy (XPS) in conjunction with a chemical-etching technique for depth profiling. The compositional structure of the interfaces obtained in the SiO2/native oxide/InSb system is derived on the basis of an intensity analysis of XPS spectra. Thermal oxidation of the InSb substrate is found to result in an In-rich native oxide and excess elemental Sb at the native oxide/substrate interface.

Vasquez, R. P.↗
NASA NTRSDate not supplied

Progress Towards SiC ASICs for Extreme Temperature and Radiation Environments

This presentation describes development and demonstrations of semiconductor integrated circuits (ICs) and ceramic packaging that are arguably the most environmentally durable transistor electronics ever demonstrated. Silicon carbide (SiC) junction field effect transistor-resistor (JFET-R) ICs fabricated by NASA Glenn Research Center with two-level interconnect have successfully operated for over 1 year in 500 °C air-ambient, 60 days in 460 °C and 9.3 MPa pressure caustic Venus surface environment test chamber, and radiation exposure through 7 Mrad(Si) total ionizing dose (TID) and 86 MeV-cm2/mg heavy ion strikes. Furthermore, these ICs have also demonstrated operation from -190 °C to +812 °C (over 1000 °C temperature span) without significant change in signal (input /output) or power supply voltages. While the operating frequency and functional complexity is far below silicon-based ICs, these SiC application specific ICs (ASICs) are nevertheless becoming capable of providing unique and advantageous harsh-environment circuit functionality without cooling/sheltering overhead. With modest adjustments, the SiC JFET-R fabrication process is compatible with semiconductor mass-production tools and materials. As an initial step towards manufacture, a majority of processing steps to realize the next SiC JFET-R IC prototype wafer run have been outsourced to commercial foundry. It is expected that further upscaling combined with technology transfer to commercial production will lower investment and risk barriers to useful application deployment.

high temperature↗
NASA NTRS1991

Comparative study of bolometric and non-bolometric switching elements for microwave phase shifters

The performance of semiconductor and high critical temperature superconductor switches is compared as they are used in delay-line-type microwave and millimeter-wave phase shifters. Such factors as their ratios of the off-to-on resistances, parasitic reactances, power consumption, speed, input-to-output isolation, ease of fabrication, and physical dimensions are compared. Owing to their almost infinite off-to-on resistance ratio and excellent input-to-output isolation, bolometric superconducting switches appear to be quite suitable for use in microwave phase shifters; their only drawbacks are their speed and size. The SUPERFET, a novel device whose operation is based on the electric field effect in high critical temperature ceramic superconductors is also discussed. Preliminary results indicate that the SUPERFET is fast and that it can be scaled; therefore, it can be fabricated with dimensions comparable to semiconductor field-effect transistors.

Tabib-Azar, Massood↗
NASA NTRS1991

Comparative study of bolometric and non-bolometric switching elements for microwave phase shifters

The performance of semiconductor and high critical temperature superconductor switches is compared as they are used in delay-line-type microwave and millimeter-wave phase shifters. Such factors as their ratios of the off-to-on resistances, parasitic reactances, power consumption, speed, input-to-output isolation, ease of fabrication, and physical dimensions are compared. Owing to their almost infinite off-to-on resistance ratio and excellent input-to-output isolation, bolometric superconducting switches appear to be quite suitable for use in microwave phase shifters; their only drawbacks are their speed and size. The SUPERFET, a novel device whose operation is based on the electric field effect in high critical temperature ceramic superconductors is also discussed. Preliminary results indicate that the SUPERFET is fast and that it can be scaled; therefore, it can be fabricated with dimensions comparable to semiconductor field-effect transistors.

Tabib-Azar, Massood↗
NASA NTRSDate not supplied

Progress Towards Prolonged Deployment of SiC JFET-R ICs Into Previously Inaccessible Hostile Environments

This invited presentation describes demonstration of semiconductor integrated circuits (ICs) and ceramic packaging that are arguably the most environmentally durable transistor electronics ever demonstrated. SiC junction field effect transistor-resistor (JFET-R) ICs with two-level interconnect have successfully operated for over 1 year in 500 °C air-ambient [1], 60 days in 460 °C and 9.3 MPa pressure caustic Venus surface environment test chamber [2], and radiation exposure through 7 Mrad(Si) total ionizing dose (TID) and 86 MeV-cm2/mg heavy ion strikes [3]. Furthermore, these ICs have also demonstrated operation from -190 °C to +812 °C (over 1000 °C T-span) without significant change in signal (input /output) or power supply voltages [4]. With modest adjustments, the SiC JFET-R fabrication process is compatible with semiconductor mass-production tools and materials. As an initial step towards this end, the processing that forms the SiC JFETs and resistors (without interconnect) for the NASA Glenn “Generation 12” design prototype JFET-R ICs was conducted at GE Research. Once the COVID-delayed IC interconnect and bond pad fabrication processing on these wafers is completed at NASA Glenn, the resulting chips will be packaged and oven-tested [5]. It is expected that further technology transfer to complete commercial production will lower investment and risk barriers to useful application deployment. For NASA, an initial high-value deployment is opening the Venus surface to extended missions for robotic scientific exploration.

Silicon Carbide↗
NASA NTRS2006

Graded junction termination extensions for electronic devices

A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc. These devices require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power handling capabilities. The graded junction termination extension disclosed is effective, self-aligned, and simplifies the implementation process.

Merrett, J. Neil↗
NASA NTRS2007

Graded junction termination extensions for electronic devices

A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc. These devices require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power handling capabilities. The graded junction termination extension disclosed is effective, self-aligned, and simplifies the implementation process.

Merrett, J. Neil↗