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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 127 records · Page 7
All sourcesNASA NTRSDOE OSTI
NASA NTRS1997

An Examination of Environment Perturbation Effects on Single Event Upset Rates

This paper presents an analysis of the sensitivity of single event upset (SEU) rate predictions to changes in the direct ionization-inducing environment. An examination based on the nature of the SEU rate equation is presented for the case in which the perturbation is constant across varying particle linear energy transfer (LET). It is shown that the relative variation in SEU rate is equal to the relative perturbation in flux. Results are also presented for the case in which the environment perturbations exist in small LET bins. Through this analysis it is shown that the relative variation in expected SEU rate is equal to that in flux only for the LET regime in which the product of the cross section and differential flux is maximum.

Gates, Michele M.↗
NASA NTRS1999

Effects of Cabin Upsets on Adsorption Columns for Air Revitalization

The National Aeronautics and Space Administration (NASA) utilizes adsorption technology as part of contaminant removal systems designed for long term missions. A variety of trace contaminants can be effectively removed from gas streams by adsorption onto activated carbon. An activated carbon adsorption column meets NASA's requirements of a lightweight and efficient means of controlling trace contaminant levels aboard spacecraft and space stations. The activated carbon bed is part of the Trace Contaminant Control System (TCCS) which is utilized to purify the cabin atmosphere. TCCS designs oversize the adsorption columns to account for irregular fluctuations in cabin atmospheric conditions. Variations in the cabin atmosphere include changes in contaminant concentrations, temperature, and relative humidity. Excessively large deviations from typical conditions can result from unusual crew activity, equipment malfunctions, or even fires. The research carried out under this award focussed in detail on the effects of cabin upsets on the performance of activated carbon adsorption columns. Both experiments and modeling were performed with an emphasis on the roll of a change in relative humidity on adsorption of trace contaminants. A flow through fixed-bed apparatus was constructed at the NASA Ames Research Center, and experiments were performed there by W. Scot Appel under the direction of Dr. John E. Finn. Modeling work was performed at the University of Virginia and at Vanderbilt University by W. Scot Appel under the direction of M. Douglas LeVan. All three participants collaborated in all of the various phases of the research. The most comprehensive document describing the research is the Ph.D. dissertation of W. Scot Appel. Results have been published in several papers and presented in talks at technical conferences. All documents have been transmitted to Dr. John E. Finn.

LeVan, M. Douglas↗
NASA NTRS1999

Effects of Cabin Upsets on Adsorption Columns for Air Revitalization

The National Aeronautics and Space Administration (NASA) utilizes adsorption technology as part of contaminant removal systems designed for long term missions. A variety of trace contaminants can be effectively removed from gas streams by adsorption onto activated carbon. An activated carbon adsorption column meets NASA's requirements of a lightweight and efficient means of controlling trace contaminant levels aboard spacecraft and space stations. The activated carbon bed is part of the Trace Contaminant Control System (TCCS) which is utilized to purify the cabin atmosphere. TCCS designs oversize the adsorption columns to account for irregular fluctuations in cabin atmospheric conditions. Variations in the cabin atmosphere include changes in contaminant concentrations, temperature, and relative humidity. Excessively large deviations from typical conditions can result from unusual crew activity, equipment malfunctions, or even fires. The research carried out under this award focussed in detail on the effects of cabin upsets on the performance of activated carbon adsorption columns. Both experiments and modeling were performed with an emphasis on the roll of a change in relative humidity on adsorption of trace contaminants. A flow through fixed-bed apparatus was constructed at the NASA Ames Research Center, and experiments were performed there. Modeling work was performed at the University of Virginia.

LeVan, Douglas↗
NASA NTRS2002

Method and Apparatus for Reducing the Vulnerability of Latches to Single Event Upsets

A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause the voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch. The method reduces the vulnerability of a latch to single event upsets. The latch includes a gate having an input and an output and a feedback path from the output to the input of the gate. The method includes inserting a delay into the feedback path and providing a delay in the gate.

Robert L Shuler, Jr.↗
NASA NTRS2002

Method and Apparatus for Reducing the Vulnerability of Latches to Single Event Upsets

A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause tile voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch. A method reduces the vulnerability of a latch to single event upsets. The latch includes a gate having an input and an output and a feedback path from the output to the input of the gate. The method includes inserting a delay into the feedback path and providing a delay in the gate.

Robert L Shuler Jr.↗
NASA NTRS2006

Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

SEU from heavy-ions is measured for SOI PowerPC microprocessors. Results for 0.13 micron PowerPC with 1.1V core voltages increases over 1.3V versions. This suggests that improvement in SEU for scaled devices may be reversed. In recent years there has been interest in the possible use of unhardened commercial microprocessors in space because of their superior performance compared to hardened processors. However, unhardened devices are susceptible to upset from radiation space. More information is needed on how they respond to radiation before they can be used in space. Only a limited number of advanced microprocessors have been subjected to radiation tests, which are designed with lower clock frequencies and higher internal core voltage voltages than recent devices [1-6]. However the trend for commercial Silicon-on-insulator (SOI) microprocessors is to reduce feature size and internal core voltage and increase the clock frequency. Commercial microprocessors with the PowerPC architecture are now available that use partially depleted SOI processes with feature size of 90 nm and internal core voltage as low as 1.0 V and clock frequency in the GHz range. Previously, we reported SEU measurements for SOI commercial PowerPCs with feature size of 0.18 and 0.13 m [7, 8]. The results showed an order of magnitude reduction in saturated cross section compared to CMOS bulk counterparts. This paper examines SEUs in advanced commercial SOI microprocessors, focusing on SEU sensitivity of D-Cache and hangs with feature size and internal core voltage. Results are presented for the Motorola SOI processor with feature sizes of 0.13 microns and internal core voltages of 1.3 and 1.1 V. These results are compared with results for the Motorola SOI processors with feature size of 0.18 microns and internal core voltage of 1.6 and 1.3 V.

Irom, Farokh↗
NASA NTRS2002

The contribution of diffusion to device upset cross sections

A novel technique incorporating carrier recombination, for determining the charge collection efficiency funcition is presented and applied to a realistic, 3-D, memory device to obtain the upset cross section as a function of LET and orientation of incidence.

charge collection diffusion SEU↗
NASA NTRS2002

Single event upset suspectibility testing of the Xilinx Virtex II FPGA

Heavy ion testing of the Xilinx Virtex II was conducted on the configuration, block RAM and user flip flop cells to determine their static single-event upset susceptibility using LETs of 1.2 to 60 MeVcm^2/mg. A software program specifically designed to count errors in the FPGA was used to reveal L1/e, values (the LET at which the cross section is l/e times the saturation cross-section) and single-event functional-interrupt failures.

FPGA Virtex II SEU↗
NASA NTRS2006

Application of RADSAFE to Model Single Event Upset Response of a 0.25 micron CMOS SRAM

The RADSAFE simulation framework is described and applied to model Single Event Upsets (SEU) in a 0.25 micron CMOS 4Mbit Static Random Access Memory (SRAM). For this circuit, the RADSAFE approach produces trends similar to those expected from classical models, but more closely represents the physical mechanisms responsible for SEU in the SRAM circuit.

Warren, Kevin M.↗
NASA NTRS2007

The Dangers of Failure Masking in Fault-Tolerant Software: Aspects of a Recent In-Flight Upset Event

On 1 August 2005, a Boeing Company 777-200 aircraft, operating on an international passenger flight from Australia to Malaysia, was involved in a significant upset event while flying on autopilot. The Australian Transport Safety Bureau's investigation into the event discovered that an anomaly existed in the component software hierarchy that allowed inputs from a known faulty accelerometer to be processed by the air data inertial reference unit (ADIRU) and used by the primary flight computer, autopilot and other aircraft systems. This anomaly had existed in original ADIRU software, and had not been detected in the testing and certification process for the unit. This paper describes the software aspects of the incident in detail, and suggests possible implications concerning complex, safety-critical, fault-tolerant software.

Johnson, C. W.↗
NASA NTRS2001

Apparatus for and method of eliminating single event upsets in combinational logic

An apparatus for and method of eliminating single event upsets (or SEU) in combinational logic are used to prevent error propagation as a result of cosmic particle strikes to the combinational logic. The apparatus preferably includes a combinational logic block electrically coupled to a delay element, a latch and an output buffer. In operation, a signal from the combinational logic is electrically coupled to a first input of the latch. In addition, the signal is routed through the delay element to produce a delayed signal. The delayed signal is routed to a second input of the latch. The latch used in the apparatus for preventing SEU preferably includes latch outputs and a feature that the latch outputs will not change state unless both latch inputs are correct. For example, the latch outputs may not change state unless both latch inputs have the same logical state. When a cosmic particle strikes the combinational logic, a transient disturbance with a predetermined length may appear in the signal. However, a function of the delay element is to preferably provide a time delay greater than the length of the transient disturbance. Therefore, the transient disturbance will not reach both latch inputs simultaneously. As a result, the latch outputs will not permanently change state in error due to the transient disturbance. In addition, the output buffer preferably combines the latch outputs in such a way that the correct state is preserved at all times. Thus, combinational logic with protection from SEU is provided.

Gambles, Jody W.↗
NASA NTRS2006

Monte Carlo Simulation of Proton Upsets in Xilinx Virtex-II FPGA Using a Position Dependent Q(sub crit) with PROPSET

This paper describes new software simulation code for predicting single event upset data from measured heavy ion data, using methods, code, and algorithms already reported in the open literature. The measured data that is used to compare against the results of this new simulation code has also been reported in the open literature (R. Koga, et al). The new code is not provided as part of this paper, only the methodology used in generating the code. This paper presents results of basic research, not design-to information, and is representative of other papers reported in the open literature (see paper references). Therefore, the content of this paper is suitable for being made publicly available at the IEEE conference and the resulting IEEE journal.

O'Neill, Patrick M.↗
NASA NTRS2008

Practical Application of a Subscale Transport Aircraft for Flight Research in Control Upset and Failure Conditions

Over the past decade, the goal of reducing the fatal accident rate of large transport aircraft has resulted in research aimed at the problem of aircraft loss-of-control. Starting in 1999, the NASA Aviation Safety Program initiated research that included vehicle dynamics modeling, system health monitoring, and reconfigurable control systems focused on flight regimes beyond the normal flight envelope. In recent years, there has been an increased emphasis on adaptive control technologies for recovery from control upsets or failures including damage scenarios. As part of these efforts, NASA has developed the Airborne Subscale Transport Aircraft Research (AirSTAR) flight facility to allow flight research and validation, and system testing for flight regimes that are considered too risky for full-scale manned transport airplane testing. The AirSTAR facility utilizes dynamically-scaled vehicles that enable the application of subscale flight test results to full scale vehicles. This paper describes the modeling and simulation approach used for AirSTAR vehicles that supports the goals of efficient, low-cost and safe flight research in abnormal flight conditions. Modeling of aerodynamics, controls, and propulsion will be discussed as well as the application of simulation to flight control system development, test planning, risk mitigation, and flight research.

Cunningham, Kevin↗
NASA NTRS2008

Characterizing SRAM Single Event Upset in Terms of Single and Double Node Charge Collection

A well-collapse source-injection mode for SRAM SEU is demonstrated through TCAD modeling. The recovery of the SRAM s state is shown to be based upon the resistive path from the p+-sources in the SRAM to the well. Multiple cell upset patterns for direct charge collection and the well-collapse source-injection mechanisms are then predicted and compared to recent SRAM test data.

Black, J. D.↗
NASA NTRS2006

Fault Tolerance Implementation within SRAM Based FPGA Designs based upon Single Event Upset Occurrence Rates

Emerging technology is enabling the design community to consistently expand the amount of functionality that can be implemented within Integrated Circuits (ICs). As the number of gates placed within an FPGA increases, the complexity of the design can grow exponentially. Consequently, the ability to create reliable circuits has become an incredibly difficult task. In order to ease the complexity of design completion, the commercial design community has developed a very rigid (but effective) design methodology based on synchronous circuit techniques. In order to create faster, smaller and lower power circuits, transistor geometries and core voltages have decreased. In environments that contain ionizing energy, such a combination will increase the probability of Single Event Upsets (SEUs) and will consequently affect the state space of a circuit. In order to combat the effects of radiation, the aerospace community has developed several "Hardened by Design" (fault tolerant) design schemes. This paper will address design mitigation schemes targeted for SRAM Based FPGA CMOS devices. Because some mitigation schemes may be over zealous (too much power, area, complexity, etc.. . .), the designer should be conscious that system requirements can ease the amount of mitigation necessary for acceptable operation. Therefore, various degrees of Fault Tolerance will be demonstrated along with an analysis of its effectiveness.

Berg, Melanie↗
NASA NTRS2003

Mitigating Upsets in SRAM-Based FPGAs from the Xilinx Virtex 2 Family

Static random access memory (SRAM) upset rates in field programmable gate arrays (FPGAs) from the Xilinx Virtex 2 family have been tested for radiation effects on configuration memory, block RAM and the power-on-reset (POR) and SelectMAP single event functional interrupts (SEFIs). Dynamic testing has shown the effectiveness and value of Triple Module Redundancy (TMR) and partial reconfiguration when used in conjunction. Continuing dynamic testing for more complex designs and other Virtex 2 capabilities (i.e., I/O standards, digital clock managers (DCM), etc.) is scheduled.

SEE testing↗