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At least 1,333 records · Page 74

All sources NASA NTRS DOE OSTI

DOE OSTI2017

Shape-memory polymer foam device for treating aneurysms

A system for treating an aneurysm in a blood vessel or vein, wherein the aneurysm has a dome, an interior, and a neck. The system includes a shape memory polymer foam in the interior of the aneurysm between the dome and the neck. The shape memory polymer foam has pores that include a first multiplicity of pores having a first pore size and a second multiplicity of pores having a second pore size. The second pore size is larger than said first pore size. The first multiplicity of pores are located in the neck of the aneurysm. The second multiplicity of pores are located in the dome of the aneurysm.

60 APPLIED LIFE SCIENCES↗

DOE OSTI2017

Ultra low density biodegradable shape memory polymer foams with tunable physical properties

Compositions and/or structures of degradable shape memory polymers (SMPs) ranging in form from neat/unfoamed to ultra low density materials of down to 0.005 g/cc density. These materials show controllable degradation rate, actuation temperature and breadth of transitions along with high modulus and excellent shape memory behavior. A method of m ly low density foams (up to 0.005 g/cc) via use of combined chemical and physical aking extreme blowing agents, where the physical blowing agents may be a single compound or mixtures of two or more compounds, and other related methods, including of using multiple co-blowing agents of successively higher boiling points in order to achieve a large range of densities for a fixed net chemical composition. Methods of optimization of the physical properties of the foams such as porosity, cell size and distribution, cell openness etc. of these materials, to further expand their uses and improve their performance.

36 MATERIALS SCIENCE↗

DOE OSTI2018

Processor-in-memory-and-storage architecture

A method and apparatus for performing reliable general-purpose computing. Each sub-core of a plurality of sub-cores of a processor core processes a same instruction at a same time. A code analyzer receives a plurality of residues that represents a code word corresponding to the same instruction and an indication of whether the code word is a memory address code or a data code from the plurality of sub-cores. The code analyzer determines whether the plurality of residues are consistent or inconsistent. The code analyzer and the plurality of sub-cores perform a set of operations based on whether the code word is a memory address code or a data code and a determination of whether the plurality of residues are consistent or inconsistent.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2018

Apparatus and methods for memory using in-plane polarization

A memory device includes a semiconductor layer with an in-plane polarization component switchable between a first direction and a second direction. A writing electrode is employed to apply a writing voltage to the semiconductor layer to change the in-plane polarization component between the first direction and the second direction. A reading electrode is employed to apply a reading voltage to the semiconductor layer to measure a tunneling current substantially perpendicular to the polarization direction of the in-plane polarization component. The directions of the reading voltage and the writing voltage are substantially perpendicular to each other. Therefore, the reading process is non-destructive. Thin films (e.g., one unit cell thick) of ferroelectric material can be used in the memory device to increase the miniaturization of the device.

42 ENGINEERING↗

DOE OSTI2018

Magnetoelectric memory cells with domain-wall-mediated switching

A magnetoelectric memory cell with domain-wall-mediated switching is implemented using a split gate architecture. The split gate architecture allows a domain wall to be trapped within a magnetoelectric antiferromagnetic (MEAF) active layer. An extension of this architecture applies to multiple-gate linear arrays that can offer advantages in memory density, programmability, and logic functionality. Applying a small anisotropic in-plane shear strain to the MEAF can block domain wall precession to improve reliability and speed of switching.

42 ENGINEERING↗

DOE OSTI2015

Ground-referenced single-ended memory interconnect

A system is provided for transmitting signals. The system comprises a first processing unit, a memory subsystem, and a package. The first processing unit is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. The memory subsystem is configured to include a second GRS interface circuit. The package is configured to include one or more electrical traces that couple the first GRS interface to the second GRS interface, where the first GRS interface circuit and the second GRS interface circuit are each configured to transmit a pulse along one trace of the one or more electrical traces by discharging a capacitor between the one trace and a ground network.

Dally, William J.↗

DOE OSTI2014

Optimizing TLB entries for mixed page size storage in contiguous memory

A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.

Chen, Dong↗

DOE OSTI2019

Memory node controller

A memory node controller for a node of a data processing network, the network including at least one computing device and at least one data resource, each data resource addressed by a physical address. The node is configured to couple the at least one computing device with the at least one data resource. Elements of the data processing network are addressed via a system address space. The memory node controller includes a first interface to the at least one data resource, a second interface to the at least one computing device, and a system to physical address translator cache configured to translate a system address in the system address space to a physical address in the physical address space of the at least one data resource.

96 KNOWLEDGE MANAGEMENT AND PRESERVATION↗

DOE OSTI2019

Shape memory embolectomy devices and systems

An embolectomy device comprised of an expansion unit and a support unit is disclosed. The expansion unit can be actuated in response to one or more external stimuli, and the support unit, located proximately to the expansion unit, provides a force to hold the expansion unit in place and to further induce the expansion unit's radial expansion. The radial expansion of the expansion unit causes the expansion unit to physically contact a blood clot, enabling the blood clot to be removed. In some embodiments, the expansion unit can be fabricated from a shape memory polymer foam. In some embodiments the support unit can be fabricated from any elastic material including, without limitation, shape memory alloys.

Szafron, Jason↗

DOE OSTI2021

A Memory Efficient Lock-Free Circular Queue

Hardware queues are import in many applications, such as data transfer, synchronization of concurrent modules with the need of mutual exclusion constructs. State of the art bounded (of a fixed size) lock free circular queues are implemented either by read/write atomic operations, or barrier conditions, or by separating dequeue and enqueue operations. However, these queues always require an unused element at all the times to safe-guard the front and rear pointers of the queue, so as to avoid data race conditions, which leads to the waste of memory. The waste of memory is especially disadvantageous in applications such as I/O data transfer, and image transfer between processing filters, when large element size is needed, We propose a lock-free solution of the bounded circular queue through read/write atomic operations, but without the need of an extra element in the queue. The proposed solution is implemented and verified in both Verilog and ’C’ languages. We also demonstrate its effectiveness by comparing its area and delay metrics with the implementations of other existing designs of queue.

Miniskar, Narasinga Rao↗

DOE OSTI2021

Shape-memory polymer foam device for treating aneurysms

Ortega, Jason M.↗

DOE OSTI2022

Sensitivity Study of Mini-Batch Size on a Long Short-Term Memory Network for In-situ Sensing of Core-to-shell Ratio of Microencapsulated Phase Change Materials

Microencapsulated phase change materials are being studied for applications for thermal energy storage in concentrated solar fields. During fabrication, the thickness of the encapsulation cannot be readily measured for real-time control. Therefore, a machine learning network, specifically a Long Short-Term Memory network, is being developed to estimate the ratio of the shell radius to core radius based on a one second temperature history. The mini-batch size determines how often the algorithm weights are updated during network training, and shuffle indicates whether the training data is shuffled during training. A general factorial design is used to analyze the effects of varying mini-batch size and shuffle, along with the core-to-shell ratio, on the RMSE of the response from the Long Short-Term Memory network. It was found that the network performed better for smaller core to shell ratios (less than 0.6) and had the lowest RMSE when the minibatch size was 128. The minimum RMSE found was 0.00501.

Shannon, Rebecca↗

DOE OSTI2022

Shape memory embolectomy devices and systems

59 BASIC BIOLOGICAL SCIENCES↗

DOE OSTI2022

Promoting prefetched data from a cache memory to registers in a processor

An electronic device includes a processor having a cache memory, a plurality of physical registers, and a promotion logic functional block. The promotion logic functional block promotes prefetched data from a portion of a cache block in the cache memory into a given physical register, the promoting including storing the prefetched data in the given physical register. Upon encountering a load micro-operation that loads data from the portion of the cache block into a destination physical register, the promotion logic functional block sets the processor so that the prefetched data stored in the given physical register is provided to micro-operations that depend on the load micro-operation.

Kotra, Jagadish↗

DOE OSTI2022

Generative memory for lifelong machine learning

Techniques are disclosed for training machine learning systems. An input device receives training data comprising pairs of training inputs and training labels. A generative memory assigns training inputs to each archetype task of a plurality of archetype tasks, each archetype task representative of a cluster of related tasks within a task space and assigns a skill to each archetype task. The generative memory generates, from each archetype task, auxiliary data comprising pairs of auxiliary inputs and auxiliary labels. A machine learning system trains a machine learning model to apply a skill assigned to an archetype task to training and auxiliary inputs assigned to the archetype task to obtain output labels corresponding to the training and auxiliary labels associated with the training and auxiliary inputs assigned to the archetype task to enable scalable learning to obtain labels for new tasks for which the machine learning model has not previously been trained.

Nadamuni Raghavan, Aswin↗

DOE OSTI2022

Post polymerization cure shape memory polymers

This invention relates to chemical polymer compositions, methods of synthesis, and fabrication methods for devices regarding polymers capable of displaying shape memory behavior (SMPs) and which can first be polymerized to a linear or branched polymeric structure, having thermoplastic properties, subsequently processed into a device through processes typical of polymer melts, solutions, and dispersions and then crossed linked to a shape memory thermoset polymer retaining the processed shape.

Wilson, Thomas S.↗

DOE OSTI2023

Dynamic kernel memory space allocation

A processing unit includes one or more processor cores and a set of registers to store configuration information for the processing unit. The processing unit also includes a coprocessor configured to receive a request to modify a memory allocation for a kernel concurrently with the kernel executing on the at least one processor core. The coprocessor is configured to modify the memory allocation by modifying the configuration information stored in the set of registers. In some cases, initial configuration information is provided to the set of registers by a different processing unit. The initial configuration information is stored in the set of registers prior to the coprocessor modifying the configuration information.

Gutierrez, Anthony↗

DOE OSTI2017

Development of an Integrated System for the Long-term Preservation of Records, Knowledge and Memory relating to Radioactive Waste Disposal Facilities - 17099

The Nuclear Energy Agency (NEA) has co-ordinated an international initiative to develop a common approach to the preservation of records, knowledge and long-term memory (RK and M), focused on radioactive waste disposals. The work programme has run in two phases, starting in 2011, with the current phase of the project due to be completed in 2018. Preparations for final reporting are now underway. The detailed implementation of an approach to RK and M preservation for any disposal facility will always remain a national decision. However, the NEA project has produced a 'menu' of tools and techniques that can be accessed and adapted to suit national needs. The common source of these menu components will help to ensure that the memory of the repository is kept alive, that messages to future populations can be clearly understood, and that evidence derived from the disposal environment can be properly interpreted. This paper describes the vision for implementation of the RK and M initiative within national programmes. Practical testing of some components of the menu of tools and techniques is currently underway in France, Sweden and USA, with encouraging results. Other disposal facilities, both under development or in planning, are invited to 'road test' the products and provide feedback. Refinement and maintenance of the tools remains important, and the NEA is committed to ensuring the continued accessibility and availability of the project outputs into the future. (authors)

12 MANAGEMENT OF RADIOACTIVE AND NON-RADIOACTIVE W↗