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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Experimental results from the characterization of a 32-channels mixed-signal processor for the GAPS experiment

This work describes the experimental results obtained from the characterization of a 32-channels readout ASIC that is the core of a module composed by 4 Lithium-drifted Silicon, Si(Li), detectors. The module is the building block of a tracker in an upcoming balloon experiment. The activity is carried out within the General AntiParticle Spectrometer (GAPS) international collaboration, whose objective is the indirect detection of dark matter through the detection of antiparticles present in cosmic rays at low energies. The balloon flight is foreseen in 2024 from the McMurdo station in Antarctica. The ASIC is designed in a 180 nm CMOS technology and has 32 low-noise analog readout channels featuring a dynamic compression of the signal, an 11-bit SAR ADC, and a digital back-end section responsible for channel setting and for sending digital information to the data acquisition system of the tracker. This work has a twofold goal: it intends on the one hand to verify the performance of the circuit, on the other to select at least 300 good samples to be used for the assembly of the GAPS Si(Li) tracker.

Riceputi, Elisa↗
DOE OSTI2025

A Radiation-Hard 8-Channel 15-Bit 40-MSPS ADC for the ATLAS Liquid Argon Calorimeter Readout

The custom design of a radiation-hardened, 8-channel, 40-MSPS, 15-bit resolution, 14.2-bit dynamic range, 11.4-ENOB ADC data acquisition ASIC fabricated in a commercial 65-nm triple-well CMOS technology is presented. The ADC is developed for and integrates seamlessly into the readout system for the ATLAS liquid argon (LAr) calorimeter in the high-luminosity large hadron collider (HLLHC) upgrade at CERN, which will require a total of 364 936 ADC channels. A three-stage MDAC+SAR pipelined ADC architecture was designed to meet the physics requirements and scientific goals of the ATLAS experiment. The ADC is a fully self-contained data acquisition system that includes foreground calibration, digital data processing, digital control, and supporting circuitry. The measured performance shows the ADC achieves a competitive dynamic range and SNDR, and it meets or exceeds the ATLAS analog requirements. Radiation tolerance and scalability design considerations were implemented at the device-, circuit-, and system-level. Radiation-hardening-by-design techniques used include redundancy for digital circuits, the use of MiM capacitors, and a hybrid RC-DAC for the ADC core. The ADC ASIC was demonstrated to be robust against the effects of the intense radiation expected in the HL-LHC experimental environment.

DAQ↗
DOE OSTI2023

FASDA: An FPGA-Aided, Scalable and Distributed Accelerator for Range-Limited Molecular Dynamics

Conducting long-term simulations of small molecules using Molecular Dynamics (MD) is crucial in drug design. However, traditional methods to accelerate the process including ASICs or GPUs, have limitations. ASICs are difficult to access, while publicly accessible GPU packages for MD have issues with more GPUs when processing small molecules, causing decreased performance. Conversely, FPGAs are renowned for their scalability and have been commonly used as accelerators for various applications, making them suitable for the task. Moreover, with the availability of FPGAs in the cloud, pharmaceutical developers can now access FPGA devices. The only missing piece is a design deployed for MD acceleration. Therefore, we present FASDA, the first FPGA-based MD accelerator available for community development. FASDA is designed to evaluate range-limited MD, which is the most resource-intensive and computationally demanding component in MD. It outperforms the state of-the-art GPU solution by 4.67x, significantly reducing the time for MD in drug design.

Wu, Chunshu↗
DOE OSTI2025

SpacelyProject/spacely-docs

Spacely is an open-source framework for the post-silicon validation of analog, digital, and mixed-signal ASICs (Application-Specific Integrated Circuits) which maximizes the reuse of hardware and software, reducing the time taken to achieve meaningful test results. Spacely specifically addresses the needs of small, flexible ASIC design teams commonly found in academia or research institutions. Spacely was originally developed at Fermi National Accelerator Laboratory.

Quinn, Adam [Fermi National Accelerator Laboratory↗
DOE OSTI2022

A MEMS Gyroscope for Reliable Long Duration Measurement While Drilling at 300°C

The 300°C Microelectromechanical system (MEMS) gyroscope project aims to contribute to DOE’s goal of increased geothermal drilling efficiency by 2025 through the development of a 300°C MEMS gyroscope for Measurement While Drilling (MWD). At the conclusion of the 2-year project, the team will develop a 300°C capable MEMS gyroscope containing GE’s patented Multi-Ring Gyroscope Transducer (MRGT) design, custom Silicon-On-Insulator (SOI) based frontend and feedback control electronics, and with demonstrated functionality and lifetime beyond 1000 hours. The project is divided into two budget periods with Go/No-Go decision at the end of the first budget period. The goal for the first budget period is to establish the feasibility of the MRGT and electronics design for meeting the 300°C performance requirements. The goal for the second budget period is to integrate the MRGT with the SOI-based application specific integrated circuit (ASIC) and demonstrate capability to operate at 300°C for 1000 hours. In Budget Period 1 we met the phase 1 goal. We successfully validated the combined MRG, electronics and packaging capability entitlement to achieving 0.5 degrees azimuth uncertainty while enabling operation at significantly higher temperatures than the state-of-the-art. In Budget Period 2, we successfully completed the integration of the MRGT and ASIC with associated high temperature, high reliability packaging to demonstrate the performance and functionality of the integrated gyroscope across the temperature range from room temperature to at 300°C. Furthermore, the team demonstrated operating life of >1,000 hours at 300°C, thus providing a validation of application-relevant lifetime capability.

15 GEOTHERMAL ENERGY↗
DOE OSTI2023

The Regenerative Current Mirror: A Very Low Power Front-End Amplifier for Silicon Pixel Detectors

In pixelized detectors, reducing power consumption in the front- end ASIC chips becomes a crucial demand. Optimization based on mature pre-amplifier schemes today is unlikely to bring sufficient improvements. A new CMOS front-end gain stage topology with very low power consumption called regenerative current mirror is developed to fulfill the demand. The circuit takes advantage of high-speed performance of current amplification while operating with relatively low bias current. The regenerative current mirror uses a NMOS current mirror and a PMOS current mirror, both with nominal gain of 1, to form a loop-back topology that provides a positive feedback. An NMOS FET with an external adjustable voltage applied to it gate terminal is used to limit open loop gain of the current mirrors to be slightly lower than 1. This yields a net gain of the positive feedback loop to be much larger than 1 while operating the current mirrors under relatively low bias currents. Simulation shows that in 65 nm fabrication process, the power consumption of the gain stages suitable for silicon pixel detectors can be controlled < 10 micro-Watts per channel. Another novel low-power circuit called Pseudo-Thyristor presented in another document will replace traditional discriminator and the Regenerative Current Mirror plus Pseudo- Thyristor will provide a full solution for the silicon pixel low-power frontend ASIC.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2022

Highly Segmented Silicon Strip Detectors for Radiation Detection (LDRD Final Report)

Large area highly segmented silicon strip detectors were investigated for use in applied radiation detection applications. Two ASIC-based readout electronics solutions were tested for compatibility. During the analysis, it was determined that significant computational resources and highly specialized firmware are required to reconstruct the data into a meaningful data stream for generalized spectroscopic performance. Future investment in the technology and careful choice of readout ASIC is expected to demonstrate relevance in measuring high activity samples.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

(U) STATEMENT OF WORK, UCD RadHard Collaboration

The following subcontract engages UC Davis (UCD) to collaborate with Lawrence Livermore National Laboratory (LLNL) on the design and analysis of microelectronic circuits (macrocells). As part of the proposed statement of work UCD will be given access to information that is export controlled. Within this statement of work UCD is to acquire and install any applicable foundry PDK(s) and collaborate with LLNL on the design of new macrocells and assist in making improvements to existing macrocells as well as the design of ASICs using collections of macrocells. The intent is to increase the application space of the existing LLNL macrocell library and demonstrate the use of the macrocell library, including new designs, by making reference design ASICs.

42 ENGINEERING↗
DOE OSTI2025

PSEC5 Physical Verification

Ultra-Fast timing detectors, having a time resolution of 10pSec or less, are becoming increasingly important for many scientific disciplines, including High Energy Physics, Nuclear Physics, Medical Imaging and more. When developing ultra-fast detectors such as MCPs, LAPPDs, LGADs, SNSPDs, it is necessary to have access to a readout system that is low power, can support many channels and is cost effective. The PSEC5 chip was an application specific integrated circuit (ASIC) developed by the pioneering group of Prof. Henry Frisch at University of Chicago and micro electronic engineers at Fermi National Accelerator Laboratory. Three boards were designed, two to implement the readout system for an LAPPD and one to only characterize the PSEC1 chip. The main goal of the project shifted to setting up a testing environment to focus on the characterization of the chip. My student and I tested and characterized this ASIC using the third chip-on-board printed circuit board. Results show the successful fabrication and operation of some of the key building blocks and lead to the suggestions on modification for the second iteration of the chip.

Rico Aniles, H. D. [Unlisted]↗
DOE OSTI2026

Pixel-Strip Module Testing and Performance Analysis for the CMS Phase-2 Outer Tracker Upgrade

In response to the demanding environment of the High-Luminosity Large Hadron Collider (HL-LHC), the Compact Muon Solenoid (CMS) Experiment's Outer Tracker is being replaced with a lighter, higher-granularity, radiation-tolerant silicon detector capable of providing tracking information directly to the Level-1 trigger system. The new Outer Tracker consists of Pixel-Strip (PS) and Strip-Strip (2S) transverse momentum (pT) modules, which are assembled and tested at, among other centers, Fermilab's Silicon Detector Facility. PS modules consist of a pixel sensor, a strip sensor, and multiple application-specific integrated circuits (ASICs). This poster studies the performance of MaPSAs, silicon macro-pixel sensors bump-bonded to 16 macro-pixel ASICS. It presents the testing procedures for MaPSAs and MaPSA-strip sensor sub-assemblies, as well as the results of calibration and performance studies of two PS modules before and after irradiation. These results assess the impact of irradiation on module performance, providing insight into the modules' expected performance in the HL-LHC environment.

Kimrey, Emerson [Scripps College]↗
DOE OSTI2025

The ATLAS Inner Tracker Strip Detector System for the Phase-II Large Hadron Collider Upgrade

ATLAS is currently preparing for the HL-LHC upgrade, with an all-silicon Inner Tracker (ITk) that will replace the current Inner Detector. The ITk will feature a pixel detector surrounded by a strip detector, with the strip system consisting of four barrel layers and 12 endcap disks. After successful completion of a large-scale prototyping program, final design reviews have been completed in key areas, such as sensors, modules, front-end electronics, and ASICs. We present an overview of the strip system and highlight the final design choices of sensors, modules, and ASICs. We summarize the results achieved during prototyping and the current status of production and pre-production on various detector components, with an emphasis on QA and QC procedures.

Duden, Emily (ORCID:0000000290929344)↗
DOE OSTI2021

hls4ml: An Open-Source Codesign Workflow to Empower Scientific Low-Power Machine Learning Devices

Accessible machine learning algorithms, software, and diagnostic tools for energy-efficient devices and systems are extremely valuable across a broad range of application domains. In scientific domains, real-time near-sensor processing can drastically improve experimental design and accelerate scientific discoveries. To support domain scientists, we have developed hls4ml, an open-source software-hardware codesign workflow to interpret and translate machine learning algorithms for implementation with both FPGA and ASIC technologies. We expand on previous hls4ml work by extending capabilities and techniques towards low-power implementations and increased usability: new Python APIs, quantization-aware pruning, end-to-end FPGA workflows, long pipeline kernels for low power, and new device backends include an ASIC workflow. Taken together, these and continued efforts in hls4ml will arm a new generation of domain scientists with accessible, efficient, and powerful tools for machine-learning-accelerated discovery.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

The design and test results of A Giga-Bit Cable Receiver (GBCR) for the ATLAS Inner Tracker Pixel Detector

This paper presents the design and test results of a Gigabit Cable Receiver ASIC called GBCR for the HL-LHC upgrade of the ATLAS Inner Tracker (ITk) pixel detector. Three prototypes (GBCR1, GBCR2, and GBCR3) have been designed in the CERN-identified 65 nm CMOS technology. GBCR receives seven (GBCR2) or six (GBCR3) channels (RX) each at 1.28 Gbps from the front-end readout chip RD53B via flex cables up to 1 meter and Twinax cables up to 5 meters and sends the equalized and retimed signals to lpGBT. Both GBCR2 and GBCR3 ASICs have two transmitting channels (TX) that pre-emphasize the signals from lpGBT before sending them to RD53B through the same cables. No Single-Event Upset (SEU) is observed in any tested channels of GBCR2 in a 400 MeV proton beam. The extrapolated bit error rate for the future HL-LHC application is below 8*10^(-16), significantly below the specified BER criterion. GBCR3 is designed to improve the immunity to single-event-upset by applying the Triple Modular Redundancy (TMR) technology to all RX channels. The retimed signals from GBCR3 have less total jitter than those from GBCR2 (35 ps versus 79 ps). Each receiver channel of GBCR3 consumes 75% more power than that of GBCR2.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2026

Design and Modeling of the Charge Readout of a SiMOS Quantum Dot with a Single Electron Transistor and CryoCMOS

Single electron spin qubits trapped in SiMOS quantum dots are a promising technology for scaling to thousand- or million-qubit systems due to their compatibility with mature CMOS manufacturing processes. A readout system that combines a single electron transistor with a custom cryogenic CMOS amplification and digitization chain offers key advantages by avoiding the use of bulky RF components or room-temperature interconnects. We present design techniques and simulation results for an optimized qubit-SET cryoCMOS interface, culminating in the design of the QNDR1 ASIC, the first cryogenic readout ASIC designed under the Quandarum project, which targets the development of a many-channel spin qubit based detector for use in high energy physics.

Quinn, Adam [Fermilab] (ORCID:0009000605056371)↗
DOE OSTI2020

The CLAS12 Micromegas Vertex Tracker

The Micromegas Vertex Tracker was designed to improve upon the tracking capabilities of the baseline design of the CLAS12 spectrometer in Hall~B at Jefferson Laboratory. A Barrel Micromegas Tracker made with six concentric cylinders, each made of three 120$^\circ$-sector tiles, surrounds the Silicon Vertex Tracker, and a Forward Micromegas Tracker composed of 6 disks is placed 30~cm downstream of the liquid-hydrogen target. Both trackers sit in a 5~T solenoid magnetic field. All Micromegas elements are based on resistive technology to withstand luminosities up to $10^{35}$~cm$^{-2}$s$^{-1}$, as well as on bulk technology to enforce gain uniformity and mechanical robustness. Due to the high magnetic field, dedicated electronics have been designed and displaced $\sim$2~m away from the detectors. The electronics readout is based on the DREAM ASICs that allow sustained operation up to 20~kHz trigger rate at the maximum luminosity.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

Rate-capability of the VMM3a front-end in the RD51 Scalable Readout System

The VMM3a is an Application Specific Integrated Circuit (ASIC), specifically developed for the readout of gaseous detectors. Originally developed within the ATLAS New Small Wheel (NSW) upgrade, it has been successfully integrated into the Scalable Readout System (SRS) of the RD51 collaboration. This allows, to use the VMM3a also in small laboratory set-ups and mid-scale experiments, which make use of Micro-Pattern Gaseous Detectors (MPGDs). As part of the integration of the VMM3a into the SRS, the readout and data transfer scheme was optimised to reach a high rate-capability of the entire readout system and profit from the VMM3a's high single-channel rate-capability of 3.6Mhits/s. The optimisation focused mainly on the handling of the data output stream of the VMM3a, but also on the development of a trigger-logic between the front-end cards and the DAQ computer. In this article, two firmware implementations of the non-ATLAS continuous readout mode are presented, as well as the implementation of the trigger-logic. Afterwards, a short overview on X-ray imaging results is presented, to illustrate the high rate-capability from an application point-of-view.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2025

SALSA: a new versatile readout chip for MPGD detectors

The SALSA chip is a future readout ASIC foreseen for the MPGD detectors, developed in the framework of the EIC collider project, to equip the MPGD trackers of the EPIC experiment. It is designed to be versatile, to be adapted to other usages of MPGD detectors like TPC or photon detectors. It integrates a frontend block and an ADC for each of the 64 channels, associated to a configurable DSP processor meant to correct data and reduce the raw data flux to limit the output bandwidth. It will be compatible with the continuous readout foreseen for the EPIC DAQ, but will also work in a triggered environment. Several prototypes are already produced in order to qualify the different blocks of the chip, in particular the frontend, the ADC and the clock generation. The next 32-channel prototype is currently under development and is planed to be produced in 2025. In conclusion, the final prototype will be produced and tested from 2026 for a production of the SALSA chip at the horizon of 2027.

Data processing↗
DOE OSTI2023

VeryFastCCD: a high frame rate soft X-ray detector

Direct X-ray detection in silicon has been transformative for scattering experiments in biology and materials science. While bump-bonded hybrid pixels have been attractive for hard X-ray detection, the challenge for single photon soft X-ray detection is sufficiently low noise. CCD structures on thick, high-resistivity silicon have been successfully used as sensors over the range of soft to hard X-rays at storage rings and FELs. The VeryFastCCD is a high frame rate, column-parallel CCD sensor with 48 μm pixels. Combined with 256-channel custom readout ASICs, frame rates of 5–10 kHz have been achieved with readout noise as low as 20 e and full-well capacity >4 × 10 5 e/pixel. Thin (10 nm and 100 nm) entrance window contact processes have also been developed which provide >85% quantum efficiency for 285 eV X-rays. Systems are currently being developed for several beamlines at the upgraded Advanced Light Source.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗