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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
NASA NTRS1995

Weaves as an Interconnection Fabric for ASIM's and Nanosatellites

Many of the micromachines under consideration require computer support, indeed, one of the appeals of this technology is the ability to intermix mechanical, optical, analog, and digital devices on the same substrate. The amount of computer power is rarely an issue, the sticking point is the complexity of the software required to make effective use of these devices. Micromachines are the nano-technologist's equivalent of 'golden screws'. In other words, they will be piece parts in larger assemblages. For example, a nano-satellite may be composed of stacked silicon wafers where each wafer contains hundreds to thousands of micromachines, digital controllers, general purpose computers, memories, and high-speed bus interconnects. Comparatively few of these devices will be custom designed, most will be stock parts selected from libraries and catalogs. The novelty will lie in the interconnections. For example, a digital accelerometer may be a component part in an adaptive suspension, a monitoring element embedded in the wrapper of a package, or a portion of the smart skin of a launch vehicle. In each case, this device must inter-operate with other devices and probes for the purposes of command, control, and communication. We propose a software technology called 'weaves' that will permit large collections of micromachines and their attendant computers to freely intercommunicate while preserving modularity, transparency, and flexibility. Weaves are composed of networks of communicating software components. The network, and the components comprising it, may be changed even while the software, and the devices it controls, are executing. This unusual degree of software plasticity permits micromachines to dynamically adapt the software to changing conditions and allows system engineers to rapidly and inexpensively develop special purpose software by assembling stock software components in custom configurations.

Gorlick, Michael M.↗
NASA NTRS1992

New inertial actuator provides isolation and stabilization in microgravity conditions

Experiments in materials and fluids processing have been conducted, or are planned, that take advantage of the low-g environment offered by space-based platforms. While the specific goals of the experiments vary, a common objective is to see improved results from the processes over those that would be obtained from similar ground-based experiments. While the space-based processing environment does offer a low-g environment, it is not disturbance free. Results of experiments already conducted, particularly those in manned vehicles, show that spacecraft induced disturbances still limit what can be achieved in materials processing. The duration of actual micro-g level environments is shorter than desired and periods of milli-g activity levels are not uncommon. While small scale experiments can be configured to overcome some of the vehicle disturbance sources, larger scale processing devices and commercial activities will require alternative methods to reduce the influences of spacecraft vibrations. Applied Technology Associates, Inc., (ATA), in cooperation with NASA Lewis Research Center, is developing hardware to provide a sustained micro-g experiment environment. This work is being sponsored under a Small Business Innovation Research (SBIR) program, which is currently in the Phase 2 development stage. ATA's approach is based on an inertial actuator, which when used as part of a closed-loop stabilization system, rejects unwanted disturbances to the experiment package. A prototype of the actuator has been fabricated and used in a laboratory demonstration to prove the principle of operation. ATA's presentation emphasized the development and testing of the Digital Materials Processing Experiment (DAMPER) inertial actuator. Physical and performance characteristics of the device are presented. Technical issues, including further optimization of the actuator's performance and plans for additional laboratory experiments, are also covered.

Blackburn, John↗
NASA NTRS1989

Gallium arsenide processing for gate array logic

The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

Cole, Eric D.↗
NASA NTRS1998

Design and Specification of Optical Bandpass Filters for Hubble Space Telescope (HST) Advanced Camera for Surveys (ACS)

Advanced optical bandpass filters for the Hubble Space Telescope (HST) Advanced Camera for Surveys (ACS) have been developed on a filter-by-filter basis through detailed studies which take into account the instrument's science goals, available optical filter fabrication technology, and developments in ACS's charge-coupled-device (CCD) detector technology. These filters include a subset of filters for the Sloan Digital Sky Survey (SDSS) which are optimized for astronomical photometry using today's charge-coupled-devices (CCD's). In order for ACS to be truly advanced, these filters must push the state-of-the-art in performance in a number of key areas at the same time. Important requirements for these filters include outstanding transmitted wavefront, high transmittance, uniform transmittance across each filter, spectrally structure-free bandpasses, exceptionally high out of band rejection, a high degree of parfocality, and immunity to environmental degradation. These constitute a very stringent set of requirements indeed, especially for filters which are up to 90 mm in diameter. The highly successful paradigm in which final specifications for flight filters were derived through interaction amongst the ACS Science Team, the instrument designer, the lead optical engineer, and the filter designer and vendor is described. Examples of iterative design trade studies carried out in the context of science needs and budgetary and schedule constraints are presented. An overview of the final design specifications for the ACS bandpass and ramp filters is also presented.

Leviton, Douglas B.↗
NASA NTRS1995

Solid-state image sensor with focal-plane digital photon-counting pixel array

A photosensitive layer such as a-Si for a UV/visible wavelength band is provided for low light level imaging with at least a separate CMOS amplifier directly connected to each PIN photodetector diode to provide a focal-plane array of NxN pixels, and preferably a separate photon-counting CMOS circuit directly connected to each CMOS amplifier, although one row of counters may be time shared for reading out the photon flux rate of each diode in the array, together with a buffer memory for storing all rows of the NxN image frame before transfer to suitable storage. All CMOS circuitry is preferably fabricated in the same silicon layer as the PIN photodetector diode for a monolithic structure, but when the wavelength band of interest requires photosensitive material different from silicon, the focal-plane array may be fabricated separately on a different semiconductor layer bump-bonded or otherwise bonded for a virtually monolithic structure with one free terminal of each diode directly connected to the input terminal of its CMOS amplifier and digital counter for integration of the photon flux rate at each photodetector of the array.

Fossum, Eric R.↗
NASA NTRS1973

Digital capacitance measuring system

The hardware phase of a digital capacitance measuring system is presented with the major emphasis placed on the electrical design and operation. Test results are included of the three units fabricated. The system's interface is applicable to existing requirements for the space shuttle vehicle.

Source record↗
NASA NTRS1974

A membrane page composer - Further developments

Membrane page composers were made and were evaluated in a simulated holographic optical memory system. Calculated and experimentally determined electromechanical and optical characteristics of the circular membrane light valves used on the arrays are shown to be in close agreement. Several operating prototypes of 8 x 8 and 16 x 16 elements were produced. Measurements were made of switching time, optical contrast, and dynamic storage time of many cells on the devices. Digital patterns were stored in the arrays. The performance required of the page composer as a component of an optical memory system is considered. The fabrication techniques used can be easily extended to larger arrays.

Cosentino, L. S.↗
NASA NTRS1976

Quiet Clean Short-haul Experimental Engine (QCSEE) preliminary under the wing flight propulsion system analysis report

The preliminary design and installation of high bypass, geared turbofan engine with a composite nacelle forming the propulsion system for a short haul passenger aircraft are described. The technology required for externally blown flap aircraft with under the wing (UTW) propulsion system installations for introduction into passenger service in the mid 1980's is included. The design, fabrication, and testing of this UTW experimental engine containing the required technology items for low noise, fuel economy, with composite structure for reduced weight and digital engine control are provided.

Howard, D. F.↗
NASA NTRSDate not supplied

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

At HiTEC2018, NASA Glenn Research Center reported the first demonstration of yearlong 500°C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021submissionupdateson-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11and near 3000 transistors/chip for Gen. 12 aremade possibleby reductions in minimum layout feature sizes (including resistorwidth shrinkage from 6 μm to 2μm) coupled with enlarged die size (from 3x3 mm to 5x5mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM)and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequentGen. 12 fabrication runcurrentlyin progress.

Silicon Carbide↗
NASA NTRS1976

A precision star tracker utilizing advanced techniques and materials

An image dissector star tracker has been developed which operates in the photon counting mode making it possible to utilize all digital electronics. A unique pulse processing circuit allows bright stars to be tracked as well as dim stars. Thermal mechanical stability has been greatly enhanced by fabricating a housing with graphite/epoxy composite material with a linear coefficient of thermal expansion near zero. Test results indicate the +10 Mv stars can be acquired and tracked, while position variation with star intensity is less than 2 arc seconds from 2.5 Mv to +10 Mv. The noise equivalent angle for a +8 Mv star is 3 arc seconds. Polynominal correction for remaining cross-coupling and nonlinearity reduced error over total 1 x 1 deg field to 1.5 arc seconds.

Gates, R. F.↗
NASA NTRS1981

Forming electrical interconnections through semiconductor wafers

An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

Anthony, T. R.↗
NASA NTRSDate not supplied

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

At HiTEC 2018, NASA Glenn Research Center reported the first demonstration of yearlong 500 °C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021 submission updates on-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11 and near 3000 transistors/chip for Gen. 12 are made possible by reductions in minimum layout feature sizes (including resistor width shrinkage from 6 µm to 2 µm) coupled with enlarged die size (from 3 x 3 mm to 5 x 5 mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM) and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequent Gen. 12 fabrication run currently in progress.

silicon carbide↗
NASA NTRS2005

Multifunctional Logic Gate Controlled by Temperature

A complementary metal oxide/semiconductor (CMOS) electronic circuit has been designed to function as a NAND gate at a temperature between 0 and 80 deg C and as a NOR gate at temperatures from 120 to 200 C. In the intermediate temperature range of 80 to 120 C, this circuit is expected to perform a function intermediate between NAND and NOR with degraded noise margin. The process of designing the circuit and the planned fabrication and testing of the circuit are parts of demonstration of polymorphic electronics a technological discipline that emphasizes designing the same circuit to perform different analog and/or digital functions under different conditions. In this case, the different conditions are different temperatures.

Stoica, Adrian↗
NASA NTRS1972

Communications terminal breadboard

A baseline design is presented of a digital communications link between an advanced manned spacecraft (AMS) and an earth terminal via an Intelsat 4 type communications satellite used as a geosynchronous orbiting relay station. The fabrication, integration, and testing of terminal elements at each end of the link are discussed. In the baseline link design, the information carrying capacity of the link was estimated for both the forward direction (earth terminal to AMS) and the return direction, based upon orbital geometry, relay satellite characteristics, terminal characteristics, and the improvement that can be achieved by the use of convolutional coding/Viterbi decoding techniques.

Source record↗
NASA NTRSDate not supplied

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRSDate not supplied

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRS2023

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRS1993

Fiber optic and laser sensors X; Proceedings of the Meeting, Boston, MA, Sept. 8-11, 1992

Topics addressed include acoustic and pressure sensors; fiber optic gyros; electric and magnetic field sensors; bend, strain, and temperature sensors; industrial applications of sensors; and processing techniques. Particular attention is given to fiber optic interferometric acoustic sensors for wind tunnel applications, polished coupler and resonator fabrication, second-harmonic detection for rotation sensing in fiber optic gyros, simplified control theory in closed-loop fiber optic gyroscopes, and a Fabry-Perot sensor with digital signal processing for the measurement of magnetostriction. Also discussed are a Bragg fiber laser sensor, commercialization of fiber optic strain gauge systems, thermal ignition in hazardous environments due to stray light from optical fibers, a system for absolute measurements by interferometric sensors, and high-performance interferometric demodulation techniques.

Udd, Eric↗