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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
NASA NTRS2016

IC 3639 - A New Bona Fide Compton-Thick AGN Unveiled By NuSTAR

We analyze high-quality NuSTAR observations of the local (z = 0.011) Seyfert 2 active galactic nucleus (AGN) IC 3639, in conjunction with archival Suzaku and Chandra data. This provides the first broadband X-ray spectral analysis of the source, spanning nearly two decades in energy (0.5-30 keV). Previous X-ray observations of the source below 10 keV indicated strong reflection/obscuration on the basis of a pronounced iron fluorescence line at 6.4 keV. The hard X-ray energy coverage of NuSTAR, together with self-consistent toroidal reprocessing models, enables direct broadband constraints on the obscuring column density of the source. We find the source to be heavily Compton-thick (CTK) with an obscuring column in excess of 3.6 x 10(exp 24) cm(exp −2), unconstrained at the upper end. We further find an intrinsic 2-10 keV luminosity of log(sub 10) (L(sub 2-10 keV) [erg s(exp -1)])= 43.4(+0.6/-1.1) to 90% confidence, almost 400 times the observed flux, and consistent with various multiwavelength diagnostics. Such a high ratio of intrinsic to observed flux, in addition to an Fe-K(alpha) fluorescence line equivalent width exceeding 2 keV, is extreme among known bona fide CTK AGNs, which we suggest are both due to the high level of obscuration present around IC 3639. Our study demonstrates that broadband spectroscopic modeling with NuSTAR enables large corrections for obscuration to be carried out robustly and emphasizes the need for improved modeling of AGN tori showing intense iron fluorescence.

galaxies: active – galaxies: nuclei – galaxies↗
NASA NTRS2018

Demonstration of 4H-SiC JFET Digital ICs Across 1000 °C Temperature Range Without Change to Input Voltages

Operational testing of prototype 4H-SiC JFET ICs across an unrivaled ambient temperature span in excess of 1000 °C, from -190 °C to +812 °C, has been demonstrated without any change/adjustment of input signal levels or power supply voltages. This unique ability is expected to simplify infusion of this IC technology into a broader range of beneficial applications.

Neudeck, Philip G.↗
NASA NTRS2023

Processing Choices for Achieving Long Term IC Operation at 500° C

The prospects for beneficial infusion of integrated circuits (ICs) into previously inaccessible extreme-temperature application environments has increased with recent NASA Glenn demonstrations of 4H-SiC Junction Field Effect Transistor & Resistor (JFET-R) chips functioning for over a year at 500 °C in air ambient [1]. This paper focuses on fabrication process choices believed key to demonstrated 500 °C durability that must be considered when porting this uniquely durable IC capability into commercial foundry manufacturing.

SiC, JFET, Integrated Circuits, High-Temperature, ↗
NASA NTRSDate not supplied

Early Burn-In Parasitic Conduction in 500 °C Durable SiC JFET ICs

All prior reports of long-term 500 °C operation of SiC JFET-R ICs have noted the existence of an initial “burn-in” period of changes in measured electrical characteristics for the first few hundred hours oven-testing. This work reports measurements of “burn-in parasitic MOSFET conduction” that can substantially impact the performance of some circuits during initial heat-up of JFET ICs, but then subsequently disappears after a few hours of operation at 500 °C. The behavior appears generally consistent with the known MOS phenomenon of bias-temperature driven redistribution of mobile ionic contamination. Approaches for further mitigating this initial burn-in conduction mechanism are discussed.

silicon carbide↗
NASA NTRSDate not supplied

Early Burn-In Parasitic Conduction in 500 °C Durable SiC JFET ICs

All prior reports of long-term 500 °C operation of SiC JFET-R ICs have noted the existence of an initial “burn-in” period of changes in measured electrical characteristics for the first few hundred hours oven-testing. This work reports measurements of “burn-in parasitic MOSFET conduction” that can substantially impact the performance of some circuits during initial heat-up of JFET ICs, but then subsequently disappears after a few hours of operation at 500 °C.

silicon carbide↗
DOE OSTI2021

Monolithic Integration of Lateral HV Power MOSFET with LV CMOS for SiC Power IC Technology

This paper reports the design and process flow for monolithic integration of lateral high voltage (HV) power MOSFET with low voltage (LV) CMOS circuits for SiC Power IC technology. The reported devices and circuits are fabricated on a N-/N+ 4H-SiC substrate at 150mm, production grade- Analog Devices Inc. (ADI) Hillview fabrication facility located in San Jose. Here, the static performance characteristics of HV NMOS and LV CMOS are reported. For future high temperature applications, the static performances are fully characterized and are reported up to 200oC. Finally, to validate the fabricated CMOS, a 5-stage ring oscillator is also demonstrated.

4H-SiC↗