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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
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NASA NTRS2021

A Low-Memory Spectral-Correlation Analyzer for Digital QAM-SRRC Waveforms

Cyclostationary signal processing (CSP) provides the ability to estimate received waveforms' statistical features blindly. Quadrature amplitude modulated (QAM) waveforms, when filtered by the square-root-raised cosine (SRRC) pulse shape function, have cyclic features that CSP can exploit to detect waveform parameters such as symbol rate (SR) and center frequency (CF). The estimation of these SR-CF pairs enables a cognitive radio (CR) to perform spectrum sensing techniques such as spectrum sharing and interference mitigation. Here, we investigate a field-programmable gate array (FPGA) application of a blind symbol rate-center frequency estimator. First, this study provides a background on the theory behind the cyclic spectral density function (CSD), spectral correlation analyzers (SCA), and spectrum sensing. Following this is a discussion on the motivation for CubeSat spectrum sensing. An SCA implementation for low-memory devices, such as FPGA-based CubeSat, is then describes. The paper concludes by reporting the performance characteristics of the newly developed streaming-based SCA.

FPGA↗
NASA NTRS2023

P-ACTIVE Project Report

The Phase change material-based actively-tunable filter (P-ACTIVE, Dr. Hyun Jung Kim, the Principal Investigator / PI) project is a NASA Langley Research Center (LaRC)-led research endeavor that began as a NASA CIF (Center Innovation Fund) project in 2019. The goal of P-ACTIVE is to develop all-solid-state tunable optical filters that can serve as low-Size, Weight, and Power (SWaP) replacements to the ubiquitous filter wheel technology current in use, and serve as a starting point for completely new optical component technologies. By using materials commonly used in electronic memory devices, namely chalcogenide phase-change materials (PCMs), in conjunction with nanostructured surfaces with exotic, tailored optical responses (“metasurfaces”), the P-ACTIVE filters are able to tune their optical transmission/reflection behavior in real-time. Because of this new functionality, P-ACTIVE filters are highlighted for NASA science and space programs such as next generation Lidar, landing system (SLS) thermal monitoring, thermal imaging, imaging spectroscopy, and disaster monitoring (e.g., volcanic eruption observations from SmallSats). This document intends to serve as a compendium of the P-ACTIVE project. We begin by describing the project from background science and assume no prior knowledge of the subject. We then address experimental and theoretical results of P-ACTIVE device performance, as well as recent results obtained from the MISSE-14 mission related to space qualification of P-ACTIVE devices and constituent materials. We conclude with a prospective view of the P-ACTIVE technology, and discuss the potential for these filters and other similar metasurface devices to serve NASA’s mission.

metamaterial↗
NASA NTRSDate not supplied

Solid State Drive Radiation Assurance With Active Testing

Automotive and industrial grade SSDs were tested for TID and SEE response at the assembly level to investigate radiation tolerance trends and explore radiation hardness assurance best practices in commercial memory devices. SSDs were installed in passive NVMe extenders to place only the drive in the beam line. A digital I/O module connected to the test computer provided inhibit signals to block both facility beam delivery and power while attempting recovery from any device failure conditions (e.g., failed write, failed read, or unresponsive device).

Edward P Wilcox↗
NASA NTRS1982

Bubble domain technology for spacecraft onboard memory

Bubble device technologies for spacecraft onboard memory offer improved reliability and memory functional characteristics. Recent advances include Permalloy gap devices (commercially available) whose improved performance and higher density are attributable to an asymmetric chevron pattern. Secondly, an order of magnitude increase in density at less power than the Permalloy technology is possible with the ion implant technology. A third technology, the self-structured current access system, offers another order of magnitude improvement in density and data rate, and is being studied. Capacity estimates for Permalloy gap, ion implant, and self-structured current access systems are, respectively, 10 to the 8th, 10 to the 9th, and 10 to the 10th bits, and power per unit data rate efficiencies are 140, 60, and 2 W/Mbps. A flexible modular organization system, compatible with all of these device technologies, is analyzed, and, as the system is contained in a bubble, relatively simple retrofitting is foreseen.

Hayes, P. J.↗
NASA NTRS1995

High Density Memory Based on Quantum Device Technology

We explore the feasibility of ultra-high density memory based on quantum devices. Starting from overall constraints on chip area, power consumption, access speed, and noise margin, we deduce boundaries on single cell parameters such as required operating voltage and standby current. Next, the possible role of quantum devices is examined. Since the most mature quantum device, the resonant tunneling diode (RTD) can easily be integrated vertically, it naturally leads to the issue of 3D integrated memory. We propose a novel method of addressing vertically integrated bistable two-terminal devices, such as resonant tunneling diodes (RTD) and Esaki diodes, that avoids individual physical contacts. The new concept has been demonstrated experimentally in memory cells of field effect transistors (FET's) and stacked RTD's.

vanderWagt, Paul↗
NASA NTRS1971

A study of nitride devices for computer memory applications

Metal-nitride-oxide-silicon /MNOS/ capacitors act like metal-nitride-silicon /MNS/ capacitors with extra interface where sheet of charge can be stored in slow states. Flatband voltage shifts over a wide range by adjusting store charge density.

Raburn, W. D.↗
NASA NTRS2018

Near-Field Heat Transfer Enabled Nanothermomechanical Memory and Logic Devices

A thermomechanical memory/logic device is disclosed. In embodiments, the thermomechanical device includes a first thermally controlled terminal (e.g., hot terminal); a second thermally controlled terminal (e.g., cool terminal/base); a stem or other structure that can be thermally expanded connected to the cool terminal; and a thermal conductive head coupled to the stem. The head can exchange heat with the hot terminal. The stem and head are between the first thermally controlled terminal and the second thermally controlled terminal, wherein the stem expands or contracts in response to heat absorbed or given off by the thermal conductive head, causing the head to move towards the first thermally controlled terminal or towards the second thermally controlled terminal until a stable state is reached. For example, bistable thermal states can be used to implement logic states (e.g., ZERO or ONE states).

Ndao, Sidy↗
NASA NTRS2011

S-Band POSIX Device Drivers for RTEMS

This is a set of POSIX device driver level abstractions in the RTEMS RTOS (Real-Time Executive for Multiprocessor Systems real-time operating system) to SBand radio hardware devices that have been instantiated in an FPGA (field-programmable gate array). These include A/D (analog-to-digital) sample capture, D/A (digital-to-analog) sample playback, PLL (phase-locked-loop) tuning, and PWM (pulse-width-modulation)-controlled gain. This software interfaces to Sband radio hardware in an attached Xilinx Virtex-2 FPGA. It uses plug-and-play device discovery to map memory to device IDs. Instead of interacting with hardware devices directly, using direct-memory mapped access at the application level, this driver provides an application programming interface (API) offering that easily uses standard POSIX function calls. This simplifies application programming, enables portability, and offers an additional level of protection to the hardware. There are three separate device drivers included in this package: sband_device (ADC capture and DAC playback), pll_device (RF front end PLL tuning), and pwm_device (RF front end AGC control).

Lux, James P.↗
NASA NTRS1993

Rapid, Nondestructive Readout From Ferroelectric Memory

Proposed devices with nondestructive readout offer attractive alternatives for rugged, solid-state memories suitable for contactless optical addressing and parallel processing and for nonvolatile analog memories. Pulses of light from lasers induce photoresponses in ferroelectric capacitors. Magnitude and polarity of response of each capacitor indicates magnitude and polarity of remanent polarization which, in turn, represents datum stored in that memory cell.

Thakoor, Sarita↗
NASA NTRS1995

Garnet Random-Access Memory

Random-access memory (RAM) devices of proposed type exploit magneto-optical properties of magnetic garnets exhibiting perpendicular anisotropy. Magnetic writing and optical readout used. Provides nonvolatile storage and resists damage by ionizing radiation. Because of basic architecture and pinout requirements, most likely useful as small-capacity memory devices.

Katti, Romney R.↗
NASA NTRS2010

NEPP non-volatile memory : FY09 summary report

This report documents the activities and results of the fiscal year 2009 (FY09) funding for the NASA Electronic Parts and Packaging (NEPP) program for non-volatile memory (NVM) devices. The FY09 task was divided into two main efforts: 1. Development of in-house measurement capability for flash devices 2. Reliability characterization of multi-level vs. single-level flash devices The FY09 NEPP Non Volatile Memory study was organized into these two sections in recognition of the continued and increasing importance of NVM to NASA. All NASA missions use NVM for boot code storage and some limited data archiving. Space-grade NVM has lagged commercial NVM development by many orders of magnitude, however. This gap in density only continues to increase as space-grade memories remain constant in the 1–16 Mbit levels, while commercial flash-based devices shrink in size and double in capacity every 18 months. Commercial flash devices are now at the 32 Gbit level, 10,000 times denser than current NASA NVM. This FY marks the beginning of a significant technological transition in NVM for NASA. The aggressive scaling of commercial NVMs has, as a by-product, made some of the flash devices radiation-tolerant enough to be at least considered for low-level radiation environment missions [Irom 2008]. This NEPP task is focused on understanding the reliability and potential future applications of such highly scaled flash memories.

Heidecker, Jason↗
NASA NTRS2018

Error Characterization and Mitigation for 16Nm MLC NAND Flash Memory Under Total Ionizing Dose Effect

A data device includes a memory having a plurality of memory cells configured to store data values in accordance with a predetermined rank modulation scheme that is optional and a memory controller that receives a current error count from an error decoder of the data device for one or more data operations of the flash memory device and selects an operating mode for data scrubbing in accordance with the received error count and a program cycles count.

Li, Yue↗
NASA NTRS1993

Programmable DMA controller

In a data system having a memory, plural input/output (I/O) devices and a bus connecting each of the I/O devices to the memory, a direct memory access (DMA) controller regulating access of each of the I/O devices to the bus, including a priority register storing priorities of bus access requests from the I/O devices, an interrupt register storing bus access requests of the I/O devices, a resolver for selecting one of the I/O devices to have access to the bus, a pointer register storing addresses of locations in the memory for communication with the one I/O device via the bus, a sequence register storing an address of a location in the memory containing a channel program instruction which is to be executed next, an ALU for incrementing and decrementing addresses stored in the pointer register, computing the next address to be stored in the sequence register, computing an initial contents of each of the register. The memory contains a sequence of channel program instructions defining a set up operation wherein the contents of each of the registers in the channel register is initialized in accordance with the initial contents computed by the ALU and an access operation wherein data is transferred on the bus between a location in the memory whose address is currently stored in the pointer register and the one I/O device enabled by the resolver.

Hendry, David F.↗
NASA NTRS1985

Electronic device aspects of neural network memories

The basic issues related to the electronic implementation of the neural network model (NNM) for content addressable memories are examined. A brief introduction to the principles of the NNM is followed by an analysis of the information storage of the neural network in the form of a binary connection matrix and the recall capability of such matrix memories based on a hardware simulation study. In addition, materials and device architecture issues involved in the future realization of such networks in VLSI-compatible ultrahigh-density memories are considered. A possible space application of such devices would be in the area of large-scale information storage without mechanical devices.

Lambe, J.↗
NASA NTRS1983

Distributed multiport memory architecture

A multiport memory architecture is diclosed for each of a plurality of task centers connected to a command and data bus. Each task center, includes a memory and a plurality of devices which request direct memory access as needed. The memory includes an internal data bus and an internal address bus to which the devices are connected, and direct timing and control logic comprised of a 10-state ring counter for allocating memory devices by enabling AND gates connected to the request signal lines of the devices. The outputs of AND gates connected to the same device are combined by OR gates to form an acknowledgement signal that enables the devices to address the memory during the next clock period. The length of the ring counter may be effectively lengthened to any multiple of ten to allow for more direct memory access intervals in one repetitive sequence. One device is a network bus adapter which serially shifts onto the command and data bus, a data word (8 bits plus control and parity bits) during the next ten direct memory access intervals after it has been granted access. The NBA is therefore allocated only one access in every ten intervals, which is a predetermined interval for all centers. The ring counters of all centers are periodically synchronized by DMA SYNC signal to assure that all NBAs be able to function in synchronism for data transfer from one center to another.

Kohl, W. H.↗
NASA NTRS2001

An FPGA-Based Test-Bed for Reliability and Endurance Characterization of Non-Volatile Memory

Memory technologies are divided into two categories. The first category, nonvolatile memories, are traditionally used in read-only or read-mostly applications because of limited write endurance and slow write speed. These memories are derivatives of read only memory (ROM) technology, which includes erasable programmable ROM (EPROM), electrically-erasable programmable ROM (EEPROM), Flash, and more recent ferroelectric non-volatile memory technology. Nonvolatile memories are able to retain data in the absence of power. The second category, volatile memories, are random access memory (RAM) devices including SRAM and DRAM. Writing to these memories is fast and write endurance is unlimited, so they are most often used to store data that change frequently, but they cannot store data in the absence of power. Nonvolatile memory technologies with better future potential are FRAM, Chalcogenide, GMRAM, Tunneling MRAM, and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) EEPROM.

Rao, Vikram↗