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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
NASA NTRS2006

Graded junction termination extensions for electronic devices

A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc. These devices require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power handling capabilities. The graded junction termination extension disclosed is effective, self-aligned, and simplifies the implementation process.

Merrett, J. Neil↗
NASA NTRS2007

Graded junction termination extensions for electronic devices

A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc. These devices require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power handling capabilities. The graded junction termination extension disclosed is effective, self-aligned, and simplifies the implementation process.

Merrett, J. Neil↗
NASA NTRS1977

Thick-film materials for silicon photovoltaic cell manufacture

Thick film technology is applicable to three areas of silicon solar cell fabrication; metallization, junction formation, and coating for protection of screened ohmic contacts, particularly wrap around contacts, interconnection and environmental protection. Both material and process parameters were investigated. Printed ohmic contacts on n- and p-type silicon are very sensitive to the processing parameters of firing time, temperature, and atmosphere. Wrap around contacts are easily achieved by first printing and firing a dielectric over the edge and subsequently applying a low firing temperature conductor. Interconnection of cells into arrays can be achieved by printing and cofiring thick film metal pastes, soldering, or with heat curing conductive epoxies on low cost substrates. Printed (thick) film vitreous protection coatings do not yet offer sufficient optical uniformity and transparency for use on silicon. A sprayed, heat curable SiO2 based resin shows promise of providing both optical matching and environmental protection.

Field, M. B.↗
NASA NTRS1981

Apparatus and technique for pulsed electron beam annealing for solar cell production

Many of the demands of high-throughput processing of solar cells can be satisfied by transient methods using pulsed electron beams. A prototype pulsed electron beam processor for solar cell production has been built, and is intended for automated annealing of solar cell junction ion implantation at a rate of 1200-1800 silicon wafers per hour. Other applications include solar cell junctions by pulse diffusion, annealing of ion-implanted back surface fields, and pulse sintering of cell metallization.

Landis, G. A.↗
NASA NTRS1996

A 850 GHz SIS receiver employing silicon micro-machining technology

A 850 GHz superconductor-insulator-superconductor (SIS) heterodyne receiver which uses a radiofrequency tuned niobium tunnel junction fabricated on a 1 micron thick silicon nitrate membrane, is reported. From video and heterodyne measurements, it was calculated that the niobium film loss in the radiofrequency matching network is about 6.8 dB at 822 GHz. These results are approximately a factor of two higher than the theoretical loss predicted by the Mattis-Bardeen theory in the extreme anomalous limit. The junction design and the receiver configuration are described, including the mixer block, the membrane construction and the cooled optics. The performance tests using a Fourier transform spectrometer to measure the response of the radiofrequency matching network, and the SIS simulations of the receiver response to cold and hot loads, the infrared noise contribution and the overall mixer conversion efficiency, are reported. It is concluded that the receiver response is limited by the absorption loss in the radiofrequency matching network.

Kooi, J. W.↗
NASA NTRSDate not supplied

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

At HiTEC2018, NASA Glenn Research Center reported the first demonstration of yearlong 500°C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021submissionupdateson-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11and near 3000 transistors/chip for Gen. 12 aremade possibleby reductions in minimum layout feature sizes (including resistorwidth shrinkage from 6 μm to 2μm) coupled with enlarged die size (from 3x3 mm to 5x5mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM)and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequentGen. 12 fabrication runcurrentlyin progress.

Silicon Carbide↗
NASA NTRSDate not supplied

Upscaling of 500 °C Durable SiC JFET-R Integrated Circuits

At HiTEC 2018, NASA Glenn Research Center reported the first demonstration of yearlong 500 °C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021 submission updates on-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11 and near 3000 transistors/chip for Gen. 12 are made possible by reductions in minimum layout feature sizes (including resistor width shrinkage from 6 µm to 2 µm) coupled with enlarged die size (from 3 x 3 mm to 5 x 5 mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM) and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequent Gen. 12 fabrication run currently in progress.

silicon carbide↗
NASA NTRS1973

Silicon-fiber blanket solar-cell array concept

Proposed economical manufacture of solar-cell arrays involves parallel, planar weaving of filaments made of doped silicon fibers with diffused radial junction. Each filament is a solar cell connected either in series or parallel with others to form a blanket of deposited grids or attached electrode wire mesh screens.

Eliason, J. T.↗
NASA NTRS1979

Development of pulsed processes for the manufacture of solar cells

Low-energy ion implantation processes for the automated production of silicon solar cells were investigated. Phosphorus ions at an energy of 10 keV and dose of 2 x 10 to the 15th power/sq cm were implanted in silicon solar cells to produce junctions, while boron ions at 25 keV and 5 x 10 to the 15th power were implanted in the cells to produce effective back surface fields. An ion implantation facility with a beam current up to 4 mA and a production throughput of 300 wafers per hour was designed and installed. A design was prepared for a 100 mA, automated implanter with a production capacity of 100 MW sub e/sq cm per year. Two process sequences were developed which employ ion implantation and furnace or pulse annealing. A computer program was used to determine costs for junction formation by ion implantation and various furnace annealing cycles to demonstrate cost effectiveness of these methods.

Minnucci, J. A.↗
NASA NTRS1988

Molecular-Beam-Epitaxy Program

Molecular Beam Epitaxy (MBE) computer program developed to aid in design of single- and double-junction cascade cells made of silicon. Cascade cell has efficiency 1 or 2 percent higher than single cell, with twice the open-circuit voltage. Input parameters include doping density, diffusion lengths, thicknesses of regions, solar spectrum, absorption coefficients of silicon (data included for 101 wavelengths), and surface recombination velocities. Results include maximum power, short-circuit current, and open-circuit voltage. Program written in FORTRAN IV.

Sparks, Patricia D.↗
NASA NTRS1984

Deep diode arrays for X-ray detection

Temperature gradient zone melting process was used to form p-n junctions in bulk of high purity silicon wafers. These diodes were patterned to form arrays for X-ray spectrometers. The whole fabrication processes for these X-ray detectors are reviewed in detail. The p-n junctions were evaluated by (1) the dark diode I-V measurements, (2) the diode C sub I - V measurements, and (3) the MOS C-V measurements. The results showed that these junctions were linearly graded in charge distribution with low reverse bias leakage current flowing through them (few nA at -10 volts). The X-ray detection experiments showed that an FWHM of 500 eV was obtained from these diodes with a small bias of just -5 volts (for X-ray source Fe55). A theoretical model was proposed to explain the extra peaks found in the energy spectra and a very interesting point - cross talk effect was pointed out. This might be a solution to the problem of making really high resolution X-ray spectrometers.

Zemel, J. N.↗
NASA NTRS1980

Incorporation of superlattice crystal layers in multijunction solar cells

Superlattice layers are effective in decreasing the density of dislocations in lattice mismatched heterostructures at least four orders of magnitude. Hence it was proposed to utilize this feature of superlattices to alleviate the problems due to misfit dislocations generated in the regions between two or more photovoltaic collecting junctions. A further advantage is that the possibility is presented for using silicon as a low cost substrate as well as for the low band gap junction. In the test case, a silicon low gap cell was connected to a GaAs.7P.3 high gap cell through a connecting region containing a GaAs/GaP superlattice.

Blackslee, A. E.↗
NASA NTRS1985

Heavily doped polysilicon-contact solar cells

The first use of a (silicon)/heavily doped polysilicon)/(metal) structure to replace the conventional high-low junction or back-surface-field (BSF) structure of silicon solar cells is reported. Compared with BSF and back-ohmic-contact (BOC) control samples, the polysilicon-back solar cells show improvements in red spectral response (RSR) and open-circuit voltage. Measurement reveals that a decrease in effective surface recombination velocity S is responsible for this improvement. Decreased S results for n-type (Si:As) polysilicon, consistent with past findings for bipolar transistors, and for p-type (Si:B) polysilicon, reported here for the first time. Though the present polysilicon-back solar cells are far from optimal, the results suggest a new class of designs for high efficiency silicon solar cells. Detailed technical reasons are advanced to support this view.

Lindholm, F. A.↗
NASA NTRS1985

Heavy doping effects in high efficiency silicon solar cells

The use of a (silicon)/(heavily doped polysilicon)/(metal) structure to replace the conventional high-low junction (or back-surface-field, BSF) structure of silicon solar cells was examined. The results of an experimental study designed to explore both qualitatively and quantitatively the mechanism of the improved current gain in bipolar transistors with polysilicon emitter contact are presented. A reciprocity theorem is presented that relates the short circuit current of a device, induced by a carrier generation source, to the minority carrier Fermi level in the dark. A method for accurate measurement of minority-carrier diffusion coefficients in silicon is described.

Lindholm, F. A.↗
NASA NTRS1985

Front and back polysilicon-contacted silicon solar cells

The first use of a (silicon)/ (heavily doped polysilicon)/ (metal) structure to replace the conventional high-low junction (or back-surface-field, BSF) structure of silicon solar cells is reported. Compared with BSF and back-ohmic-contact control samples, the polysilicon-back solar cells show improvements in red spectral response and open-circuit voltage. Measurement reveals that a decrease in effective surface recombination velocity S is responsible for this improvement. Decreased S results for n-type (Si:As) polysilicon, consistent with past findings for bipolar transistors, and for p-type (Si:B) polysilicon, reported here for the first time. Though the present polysilicon-back solar cells are far from optimal, the results suggest a new class of designs for high efficiency silicon solar cells. Detailed technical reasons are advanced to support this view.

Lindholm, F. A.↗
NASA NTRS1987

Determination of lifetime and surface recombination velocity of p-n junction solar cells and diodes by observing transients

The unified view of transient methods for the determination of recombination lifetime tau and back surface recombination velocity S presented here for silicon solar cells and diodes attempts to define limitations of existing methods and to evolve improvements. The presence of sizable junction capacitance for silicon devices under forward voltage invalidates the use of conventional open-circuit voltage decay (OCVD) and reverse recovery. This led Green (1983) to his method of compensated open-circuit voltage decay, in which the addition of an external resistor shunting the solar cell partially corrects for the presence of the junction capacitance. Setting this resistance to zero produces an electrical short-circuit current-decay method, which has the advantage of enabling determination of both tau and S. In an alternate approach, one may insert the functional dependence of the junction capacitance on forward voltage. This new method, denoted by the acronym OCVDCAP, enables the determination of tau with apparently greater accuracy than that obtained by previous methods utilizing voltage transients. But OCVDCAP has in common with the previous methods that it determines tau only and has practical utility only for determining tau of long-base devices. This means that it is useful only for thick base regions. In principle, however, it has an advantage over short-circuit current decay: it requires only pressure contacts, not ohmic contacts, and therefore may be used to determine tau after key processing steps in manufacturing.

Lindholm, Fredrik A.↗