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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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The device specifications for an all optical bit-parallel WDM single fiber link for the cluster computer network community are intended for dissemination to the opto-electronic device research community to stimulate synergy between the two, ultimately leading to early availability of new devices to the computer network researchers.
We derive several new reformulations of the Hubeny-Rangamani-Takayanagi covariant holographic entanglement entropy formula. These include: (1) a minimax formula, which involves finding a maximal-area achronal surface on a timelike hypersurface homologous to D(A) (the boundary causal domain of the region A whose entropy we are calculating) and minimizing over the hypersurface; (2) a max V-flow formula, in which we maximize the flux through D(A) of a divergenceless bulk 1-form V subject to an upper bound on its norm that is non-local in time; and (3) a min U-flow formula, in which we minimize the flux over a bulk Cauchy slice of a divergenceless timelike 1-form U subject to a lower bound on its norm that is non-local in space. The two flow formulas define convex programs and are related to each other by Lagrange duality. For each program, the optimal configurations dynamically find the HRT surface and the entanglement wedges of A and its complement. The V-flow formula is the covariant version of the Freedman-Headrick bit thread reformulation of the Ryu-Takayanagi formula. We also introduce a measure-theoretic concept of a “thread distribution”, and explain how Riemannian flows, V-flows, and U-flows can be expressed in terms of thread distributions.
Bit threads are curves in holographic spacetimes that manifest boundary entanglement, and are represented mathematically by continuum analogues of network flows or multiflows. Subject to a density bound, the maximum number of threads connecting a boundary region to its complement computes the Ryu–Takayanagi entropy. When considering several regions at the same time, for example in proving entropy inequalities, there are various inequivalent density bounds that can be imposed. Here, we investigate for which choices of bound a given set of boundary regions can be “locked”, in other words can have their entropies computed by a single thread configuration. We show that under the most stringent bound, which requires the threads to be locally parallel, non-crossing regions can in general be locked, but crossing regions cannot, where two regions are said to cross if they partially overlap and do not cover the entire boundary. We also show that, under a certain less stringent density bound, a crossing pair can be locked, and conjecture that any set of regions not containing a pairwise crossing triple can be locked, analogously to the situation for networks.
Near-term quantum computers are primarily limited by errors in quantum operations (or gates) between two quantum bits (or qubits). A physical machine typically provides a set of basis gates that include primitive 2-qubit (2Q) and 1-qubit (1Q) gates that can be implemented in a given technology. 2Q entangling gates, coupled with some 1Q gates, allow for universal quantum computation. In superconducting technologies, the current state of the art is to implement the same 2Q gate between every pair of qubits (typically an XX-or XY-type gate). This strict hardware uniformity requirement for 2Q gates in a large quantum computer has made scaling up a time and resource-intensive endeavor in the lab. We propose a radical idea – allow the 2Q basis gate(s) to differ between every pair of qubits, selecting the best entangling gates that can be calibrated between given pairs of qubits. This work aims to give quantum scientists the ability to run meaningful algorithms with qubit systems that are not perfectly uniform. Scientists will also be able to use a much broader variety of novel 2Q gates for quantum computing. We develop a theoretical framework for identifying good 2Q basis gates on “nonstandard” Cartan trajectories that deviate from “standard” trajectories like XX. We then introduce practical methods for calibration and compilation with nonstandard 2Q gates, and discuss possible ways to improve the compilation. To demonstrate our methods in a case study, we simulated both standard XY-type trajectories and faster, nonstandard trajectories using an entangling gate architecture with far-detuned transmon qubits. We identify efficient 2Q basis gates on these nonstandard trajectories and use them to compile a number of standard benchmark circuits such as QFT and QAOA. Furthermore, our results demonstrate an 8x improvement over the baseline 2Q gates with respect to speed and coherence-limited gate fidelity.
Understanding the causes of performance gaps between a portable programming model and a vendor-specific programming model is important for improving performance portability. This paper studies performance portability of low-bit fused general matrix-vector multiplication kernels in SYCL on vendors’ graphics processing units (GPUs). This work introduces the use case, explains the kernel implementations in detail, evaluates the performance of the CUDA, HIP, and SYCL kernels on datacenter, desktop, and laptop GPUs, and investigates the causes of performance gaps. The results show that loop unrolling, kernel dispatch overhead, and sum reduction contribute to the gaps.
SAND2024-08549O PyTorch Circuit-Aware Bit-Cell Modeling, a Python library, demonstrates circuit-aware training for analog machine learning accelerators. Built upon PyTorch, this software provides hardware-aware versions of common neural network layers to mitigate non-ideal behavior from novel hardware. The software provides accurate forward and backward pass estimates for hardware-mapped neural networks that are implemented in crossbars (arrays) that contain a non-linear transistor selector device. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525.
As we move into the exascale era, the power and energy footprints of high-performance computing (HPC) systems have grown significantly larger. Due to the harsh power and thermal conditions the system, components are exposed to extreme operating conditions. Operation of such modern HPC systems requires deep insights into long term system behavior to maintain its efficiency as well as its longevity. To help the HPC community to gain such insights, we provide double-bit errors using system telemetry data and logs collected from the Summit supercomputer, equipped with 27,648 Tesla V100 GPUs with 2nd-generation high-bandwidth memory (HBM2). The dataset relies on Nvidia XID records internally collected by GPU firmware at the time of failure occurrence, on the reboot-time logs of each Summit node, on node-level job scheduler records collected after each job termination, and on a 1Hz data rate from the baseboard management controllers (BMCs) of each Summit compute node using the OpenBMC event subscription protocol. Technical details can be found in the paper Oles et. al “Understanding GPU Memory Corruption at Extreme Scale: The Summit Case Study” ICS’24 (https://doi.org/10.1145/3650200.3656615).
Multi-bit watermarking has emerged as a promising solution for embedding imperceptible binary messages into Large Language Model (LLM)-generated text, enabling reliable attribution and tracing of malicious usage of LLMs. Despite recent progress, existing methods still face key limitations: some become computationally infeasible for large messages, while others suffer from a poor trade-off between text quality and decoding accuracy. Moreover, the decoding accuracy of existing methods drops significantly when the number of tokens in the generated text is limited, a condition that frequently arises in practical usage. To address these challenges, we propose XMark, a novel method for encoding and decoding binary messages in LLM-generated texts. The unique design of XMark’s encoder produces a less distorted logit distribution for watermarked token generation, preserving text quality, and also enables its tailored decoder to reliably recover the encoded message with limited tokens. Extensive experiments across diverse downstream tasks show that XMark significantly improves decoding accuracy while preserving the quality of watermarked text, outperforming prior methods. The code will be made publicly available upon acceptance.
Steel drill bit having terraces of teeth intersected by spiral grooves with teeth permits the boring of small holes through rock with low power. The cuttings are stored in a chamber behind the cutting head. Could be used as sampling device.
Computer switching network consists of parallel and series combinations of mod 2 adders using the minimum number of gating levels. This network minimizes the propagation time in which a sequence of pseudonoise check bits are generated.
Bit saving encoding scheme for set of monotonic numbers
Nylon router bit in an electric hand-held drill removes small quantities of cork insulation from a metal or fiber glass surface without cutting or scratching the surface.
Transmission system with degradation of binary coded data due to bit errors
Random bit errors in pulse code modulated data during telemetry data processing
Bit-plane encoding technique used for reducing redundancy in data gathered in space probes
Tape recorder flutter analysis and bit rate smoothing of digital data
Limitations imposed by demagnetizing fields on bit packing densities within thin ferromagnetic films of manganese bismuthide
Criteria for evaluating bit resolution capability of magnetic tapes for digital nonreturn-to-zero recording systems