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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

High-Mobility Hole Transport in Single-Grain PbSe Quantum Dot Superlattice Transistors

Epitaxially-fused superlattices of colloidal quantum dots (QD epi-SLs) may exhibit electronic minibands and high-mobility charge transport, but electrical measurements of epi-SLs have been limited to large-area, polycrystalline samples in which superlattice grain boundaries and intragrain defects suppress/obscure miniband effects. Systematic measurements of charge transport in individual, highly-ordered epi-SL grains would facilitate the study of minibands in QD films. Here, we demonstrate the air-free fabrication of microscale field-effect transistors (μ-FETs) with channels consisting of single PbSe QD epi-SL grains (2–7 μm channel dimensions) and analyze charge transport in these single-grain devices. The eight devices studied show p-channel or ambipolar transport with a hole mobility as high as 3.5 cm 2 V –1 s –1 at 290 K and 6.5 cm 2 V –1 s –1 at 170–220 K, one order of magnitude larger than that of previous QD solids. The mobility peaks at 150–220 K, but device hysteresis at higher temperatures makes the true mobility–temperature curve uncertain and evidence for miniband transport inconclusive.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2020

Detection of a multi–disease biomarker in saliva with graphene field effect transistors

Human carbonic anhydrase 1 (CA1) has been suggested as a biomarker for identification of several diseases including cancers, pancreatitis, diabetes, and Sjogren’s syndrome. However, the lack of a rapid, cheap, accurate, and easy-to-use quantification technique has prevented widespread utilization of CA1 for practical clinical applications. To this end, we present a label-free electronic biosensor for detection of CA1 utilizing highly sensitive graphene field effect transistors (G-FETs) as a transducer and specific RNA aptamers as a probe. The binding of CA1 with aptamers resulted in a positive shift in Dirac voltage V D of the G-FETs, the magnitude of which depended on target concentration. These aptameric G-FET biosensors showed the binding affinity (K D ) of ~2.3 ng/ml (70 pM), which is four orders lower than that reported using a gel shift assay. This lower value of K D enabled us to achieve a detection range (10 pg/ml - 100 ng/ml) which is well in line with the clinically relevant range. These highly sensitive devices allowed us to further prove their clinical relevance by successfully detecting the presence of CA1 in human saliva samples. In conclusion, the utilization of this label-free biosensor could facilitate the early stage identification of various diseases associated with changes in concentration of CAs.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2024

Statistical analysis of displacement damage in small devices from neutron and ion irradiation

Modern semiconductor devices, such as gate-all-around nanosheet field-effect transistors (GAA NS FETs), are smaller than displacement damage cascades from fission neutrons. In this regime, device failure may occur through low-probability single events, rather than by parametric degradation previously seen in larger devices. Here, we present a statistical model that predicts the probability of a damage event in a small device and the probability distribution of the magnitude, i.e., number of displacements within the device, from each event. The model is developed first for neutron irradiation and then for energetic ion irradiation. The model is consistent with results from recent experiments in which lithium-ion irradiation produced stepwise increases in subthreshold current in GAA NS FETs.

Wampler, W. R.↗
NASA NTRS1992

Remote hydrogen sensing techniques

The objective of this project is to evaluate remote hydrogen sensing methodologies utilizing metal oxide semi-conductor field effect transistors (MOS-FET) and mass spectrometric (MS) technologies and combinations thereof.

Perry, Cortes L.↗
NASA NTRS1993

On-Chip p-MOSFET Dosimetry

On-chip p-FETs were developed to monitor the radiation dose of n-well CMOS ICs by monitoring threshold voltage shifts due to radiation induced oxide and interface charge.

FETs↗
NASA NTRS2008

Efficient G(sup 4)FET-Based Logic Circuits

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Vatan, Farrokh↗
NASA NTRS1964

Put FETs to Work in Electrometers

Field-effect transistors, with their high impedance and low noise, can effectively measure very low currents. To bring the FET up to electrometer standards (so that it can measure currents of, say, 10 (sup -13) amp) the designer must know where the noise is and what to do about it.

ELECTROMETER↗
NASA NTRS2009

Efficient Multiplexer FPGA Block Structures Based on G4FETs

Generic structures have been conceived for multiplexer blocks to be implemented in field-programmable gate arrays (FPGAs) based on four-gate field-effect transistors (G(sup 4)FETs). This concept is a contribution to the continuing development of digital logic circuits based on G4FETs and serves as a further demonstration that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. Results in this line of development at earlier stages were summarized in two previous NASA Tech Briefs articles: "G(sup 4)FETs as Universal and Programmable Logic Gates" (NPO-41698), Vol. 31, No. 7 (July 2007), page 44, and "Efficient G4FET-Based Logic Circuits" (NPO-44407), Vol. 32, No. 1 ( January 2008), page 38 . As described in the first-mentioned previous article, a G4FET can be made to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer components than are required for conventional transistor-based circuits performing the same logic functions. The second-mentioned previous article reported results of a comparative study of NOT-majority-gate (G(sup 4)FET)-based logic-circuit designs and equivalent NOR- and NAND-gate-based designs utilizing conventional transistors. [NOT gates (inverters) were also included, as needed, in both the G(sup 4)FET- and the NOR- and NAND-based designs.] In most of the cases studied, fewer logic gates (and, hence, fewer transistors), were required in the G(sup 4)FET-based designs. There are two popular categories of FPGA block structures or architectures: one based on multiplexers, the other based on lookup tables. In standard multiplexer- based architectures, the basic building block is a tree-like configuration of multiplexers, with possibly a few additional logic gates such as ANDs or ORs. Interconnections are realized by means of programmable switches that may connect the input terminals of a block to output terminals of other blocks, may bridge together some of the inputs, or may connect some of the input terminals to signal sources representing constant logical levels 0 or 1. The left part of the figure depicts a four-to-one G(sup 4)FET-based multiplexer tree; the right part of the figure depicts a functionally equivalent four-to-one multiplexer based on conventional transistors. The G(sup 4)FET version would contains 54 transistors; the conventional version contains 70 transistors.

Vatan, Farrokh↗
NASA NTRS2007

G4-FETs as Universal and Programmable Logic Gates

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Johnson, Travis↗
NASA NTRS2006

Four-Quadrant Analog Multipliers Using G4-FETs

Theoretical analysis and some experiments have shown that the silicon-on-insulator (SOI) 4-gate transistors known as G4-FETs can be used as building blocks of four-quadrant analog voltage multiplier circuits. Whereas a typical prior analog voltage multiplier contains between six and 10 transistors, it is possible to construct a superior voltage multiplier using only four G4-FETs. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET). It can be regarded as a single transistor having four gates, which are parts of a structure that affords high functionality by enabling the utilization of independently biased multiple inputs. The structure of a G4-FET of the type of interest here (see Figure 1) is that of a partially-depleted SOI MOSFET with two independent body contacts, one on each side of the channel. The drain current comprises of majority charge carriers flowing from one body contact to the other that is, what would otherwise be the side body contacts of the SOI MOSFET are used here as the end contacts [the drain (D) and the source (S)] of the G4-FET. What would otherwise be the source and drain of the SOI MOSFET serve, in the G4-FET, as two junction-based extra gates (JG1 and JG2), which are used to squeeze the channel via reverse-biased junctions as in a JFET. The G4-FET also includes a polysilicon top gate (G1), which plays the same role as does the gate in an accumulation-mode MOSFET. The substrate emulates a fourth MOS gate (G2). By making proper choices of G4-FET device parameters in conjunction with bias voltages and currents, one can design a circuit in which two input gate voltages (Vin1,Vin2) control the conduction characteristics of G4-FETs such that the output voltage (Vout) closely approximates a value proportional to the product of the input voltages. Figure 2 depicts two such analog multiplier circuits. In each circuit, there is the following: The input and output voltages are differential, The multiplier core consists of four G4- FETs (M1 through M4) biased by a constant current sink (Ibias), and The G4-FETs in two pairs are loaded by two identical resistors (RL), which convert a differential output current to a differential output voltage. The difference between the two circuits stems from their input and bias configurations. In each case, provided that the input voltages remain within their design ranges as determined by considerations of bias, saturation, and cutoff, then the output voltage is nominally given by Vout = kVin1Vin2, where k is a constant gain factor that depends on the design parameters and is different for the two circuits. In experimental versions of these circuits constructed using discrete G4- FETs and resistors, multiplication of voltages in all four quadrants (that is, in all four combinations of input polarities) was demonstrated, and deviations of the output voltages from linear dependence on the input voltages were found to amount to no more than a few percent. It is anticipated that in fully integrated versions of these circuits, the deviations from linearity will be made considerably smaller through better matching of devices.

Mojarradi, Mohammad↗
NASA NTRS2009

G(sup 4)FET Implementations of Some Logic Circuits

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Mojarradi, Mohammad↗
NASA NTRS1969

Field Effect Transistor /FET/ circuit for variable gin amplifiers

Amplifier circuit using two FETs combines improved input and output impedances with relatively large signal handling capability and an immunity from adverse effects of automatic gain control. Circuit has sources and drains in parallel plus a resistive divider for signal and bias to either of the gate terminals.

Spaid, G. H.↗
DOE OSTI2022

On the Feasibility of 1T Ferroelectric FET Memory Array

To fully exploit the ferroelectric field effect transistor (FeFET) as compact embedded nonvolatile memory for various computing and storage applications, it is desirable to use a single FeFET (1T) as a unit cell and arrange the cells into an array. However, many write mechanisms for an 1T FeFET array reported in the literature are yet to be validated experimentally. In this work, we performed a comprehensive experimental characterization on the write operations in an 1T- NOR and 1T- AND array using n-channel bulk FeFETs. We discovered that: 1) the source/drain contact can only supply minority carriers (i.e., electrons) to the channel for polarization screening during the low- V TH state programming; 2) the body contact can not only supply majority carriers (i.e., holes) for efficient high- V TH state write, but also depletion charge for low- V TH state programming, though with lower efficiency; and 3) during the low/high- V TH programming, only the path that can supply negative/positive screening charges, respectively, need to respond, which necessitates the application of proper write biases on the corresponding terminal. Based on the understanding of these write mechanisms, we show the importance of localized body contact or column-wise body contact for the successful high- V TH state programming. We also show that the previously proposed C- AND write scheme fails to program the FeFET to the low- V TH state for our devices. Finally, we propose several write schemes for both 1T- AND and 1T- NOR arrays for various scenarios providing insights for choosing the appropriate write scheme, which will facilitate the adoption of 1T FeFET memory arrays for emerging applications.

FeFET↗
DOE OSTI2024

FET Junction Temperature Monitoring Using Novel On-Chip Solution

A novel junction temperature monitoring sensor is proposed and experimentally demonstrated for application in MOS-gate power devices. The sensor is created using the polycide gate electrode layer of the devices to create a temperature-sensitive resistor without any additional fabrication steps. The resistor is located on the field oxide with one end grounded at the device reference terminal to isolate it from the device current and voltage transients. It allows in-situ monitoring of the device junction temperature during active circuit operation. The technology has been implemented to monitor the junction temperature of Silicon Carbide Junction Barrier Schottky Field Effect Transistors (SiC JBSFETs) with the bi-directional FET (BiDFET).

Bidirectional switches, SiC bidirectional FET, BiD↗
NASA NTRS1990

Development of improved pyroelectric detectors. Measurements of pyroelectric material characteristics and FET characteristics

Research was undertaken to improve the detectivity of the pyroelectric detector with the ultimate goal of operation at or near the temperature-noise limit. Two general areas of investigation were undertaken: (1) to improve responsivity through the use of new materials; and (2) to reduce noise through improved field effect transistor characteristics, and improved electroding of the pyroelectric material. FET's are being obtained from various manufacturers, evaulated, and selected units tested for evaluation of characteristics critical to their use as preamplifiers with pyroelectric detectors.

Weiner, S.↗
DOE OSTI2025

Extreme Enhancement-Mode Operation Accumulation Channel Hydrogen-Terminated Diamond FETs with V th < -6 V and High on-Current

In this work, a new Field Effect Transistor device concept based on hydrogen-terminated diamond (H-diamond) is demonstrated that operates in an Accumulation Channel rather than a Transfer Doping regime. The FET devices demonstrate both extreme enhancement-mode operation and high on-current with improved channel charge mobility compared to Transfer-Doped equivalents. Electron-beam evaporated Al 2 O 3 is used on H-diamond to suppress the Transfer Doping mechanism and produce an extremely high ungated channel resistance. A high-quality H-diamond surface with an unpinned Fermi level is crucially achieved, allowing for the formation of a high-density hole accumulation layer by gating the entire device channel which is encapsulated in dual-stacks of Al 2 O 3 . Completed devices with gate/channel length of 1 µm demonstrate record threshold voltage < -6 V with on-current > 80 mA mm -1 . Carrier density and mobility figures extracted by CV analysis indicate a high 2D charge density of ≈ 2 × 10 12 cm -2 and increased hole mobility of 110 cm 2 V -1 s -1 in comparison with more traditional Transfer-Doped H-diamond FETs. These results demonstrate the most negative threshold voltage yet reported for H-diamond FETs and highlight a powerful new strategy to greatly improve carrier mobility and enable enhanced high power and high frequency diamond transistor performance.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS1991

Plasma-deposited germanium nitride gate insulators for indium phosphide metal-insulator-semiconductor field-effect transistors

Plasma-deposited germanium nitride was investigated for the first time as a possible gate insulator for InP compound semiconductor metal-insulator-semiconductor FET (MISFET) technology. The germanium nitride films were successfully deposited in a capacitively coupled parallel plate reactor at 13.56 MHz operation using GeH4/N2/NH3 and GeH4/N2 mixtures as reactant gases. The former process produced better quality films with enhanced uniformity, increased deposition rates, and increased resistivity. The breakdown field strength of the films was greater than 10 to the 6th V/cm. Auger electron spectroscopy did not indicate significant chemical composition differences between the two processes. For MISFETs with 2-micron channel lengths fabricated on InP, the device transconductance and threshold voltage for the GeH4/N2/NH3 process were 17 mS/mm and -3.6 V, respectively. The drain-source breakdown voltages were greater than 10 V.

Johnson, Gregory A.↗