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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 145 records · Page 8
All sourcesNASA NTRSDOE OSTI
DOE OSTI2026

Maximizing dynamic range and performance of anatase TiO 2 ECRAM through structure and programming

Here, in this study, we investigate the structure-dependent modulation characteristics of all-solid-state three-terminal electrochemical random-access memory (ECRAM) based on an anatase Li x TiO 2 channel. By directly comparing “asymmetric” and “symmetric” ECRAM device architectures, we reveal significant insight into the impact of a non-zero gate-drain open-circuit voltage and its influence on voltage vs. current-controlled gating. We also explore the impact of potentiation/depression write parameters on the symmetry, linearity, and dynamic range of the device response. Together, initial results from optimizing structure and programming approaches yielded unprecedented G max /G min ratios of >1,000 for ECRAM and hundreds of tunable memory states with excellent linearity and symmetry. Simulations based on these ECRAM devices further illustrate the promise of this analog memory technology, achieving near 2% classification error in the MNIST digit recognition benchmark for a range of training parameters compared to a theoretical best of 1.66% and outperforming other device models extracted from the literature.

AIHWKit↗
NASA NTRS1993

Analyzing Single-Event Gate Ruptures In Power MOSFET's

Susceptibilities of power metal-oxide/semiconductor field-effect transistors (MOSFET's) to single-event gate ruptures analyzed by exposing devices to beams of energetic bromine ions while applying appropriate bias voltages to source, gate, and drain terminals and measuring current flowing into or out of each terminal.

Zoutendyk, John A.↗
DOE OSTI2025

High Mobility and Electrostatics in GeSn Quantum Wells With SiGeSn Barriers

GeSn is an emerging material with potential applications in next‐generation integrated optoelectronics and quantum information processing. While GeSn/SiGeSn quantum wells exhibit promising optical properties, their electrical transport characteristics and governing electrostatics in gated structures remain unexplored. Heterostructure field‐effect transistors are fabricated using GeSn/SiGeSn quantum wells and electronic transport properties of 2D holes are characterized. At 2 K, heterostructure field‐effect transistors with well/barrier compositions of Ge 0.945 Sn 0.055 /Si 0.03 Ge 0.93 Sn 0.04 and Ge 0.9 Sn 0.1 /Si 0.017 Ge 0.927 Sn 0.056 , show peak mobilities of 9000 and 19 000 cm 2 /Vs, respectively, the latter setting a record for the highest mobility reported for GeSn quantum wells with a Sn concentration around 6 % or greater. Remarkably, at low carrier densities, devices with a SiGeSn barrier exhibit mobilities several times higher than previously reported for GeSn quantum wells with a Ge barrier. This higher mobility contrasts with the expectation that alloy scattering from the barrier would reduce carrier mobility. Two mechanisms based on atom probe tomography data analyses are proposed: i) unintentionally improved SiGeSn/GeSn interface and/or ii) reduced alloy scattering from short‐range order. Significant current–voltage hysteresis is observed, with the effective threshold gate voltage shifting by more than 5 V, attributed to non‐equilibrium trapped charge at various interfaces within the SiGeSn heterostructure.

GeSn↗
NASA NTRS1976

Gate assisted turn-off thyristor with cathode shunts and dynamic gate

A 1,000-V, 200-A gate-assisted turn-off thyristor (GATT) is described, whose design features include an interdigitated shunted cathode, a dynamic gate, a means for optimizing the carrier lifetime level, and a bypass diode. The device physics of gate-assisted turn-off are reviewed. Based on this, improvements in the design are described. It is shown that a prime failure mode can be eliminated and that the gate-assist signal voltage can be substantially decreased by employing a shunted cathode emitter. The test data show excellent turn-on characteristics due to the dynamic gate and the long perimeter of the edge of the main cathode. Turn-off times as short as 3 microsec are obtained. The combination of controlling the carrier lifetime with a precisely controlled and easily variable irradiation dose of high energy electrons with gate assist current provides for simple, precision tailoring of the device characteristics to the intended application.

Schlegel, E. S.↗
NASA NTRS1986

Efficient Power Amplifier for Motor Control

Pulse-width-modulated amplifier supplies high current as efficiently as low current needed for starting and running motor. Key to efficiency of motor-control amplifier is V-channel metal-oxide/semiconductor transistor Q1. Device has low saturation resistance. However, has large gate input capacitance and small margin between its turn-on voltage and maximum allowable gate-to-source voltage. Circuits for output stages overcome limitations of VMOS device.

Brown, R. J.↗
NASA NTRS2009

Assessment of SOI AND Gate, Type CHT-7408, for Operation in Extreme Temperature Environments

Electronic parts based on silicon-on-insulator (SOI) technology are finding widespread applications due to their ability to operate in harsh environments and the benefits they offer as compared to their silicon counterparts. Due to their construction, they are tailored for high temperature operation and show good tolerance to radiation events. In addition, their inherent design lessens the formation of parasitic junctions, thereby reducing leakage currents, decreasing power consumption, and enhancing speed. These devices are typically rated in temperature capability from -55 C to about +225 C, and their characteristics over this temperature range are documented in data sheets. Since electronics in some of NASA space exploration missions are required to operate under extreme temperature conditions, both cold and hot, their characteristic behavior within the full temperature spectrum must be determined to establish suitability for use in space applications. The effects of extreme temperature exposure on the performance of a new commercial-off-the-shelf (COTS) SOI AND gate device were evaluated in this work. The high temperature, quad 2-inputs AND gate device, which was recently introduced by CISSOID, is fabricated using a CMOS SOI process. Some of the specifications of the CHT-7408 chip are listed in a table. By supplying a constant DC voltage to one gate input and a 10 kHz square wave into the other associated gate input, the chip was evaluated in terms of output response, output rise (t(sub r)) and fall times (tf), and propagation delays (using a 50% level between input and output during low to high (tPLH) and high to low (tPHL) transitions). The supply current of the gate circuit was also obtained. These parameters were recorded at various test temperatures between -195 C and +250 C using a Sun Systems environmental chamber programmed at a temperature rate of change of 10 C/min. In addition, the effects of thermal cycling on this chip were determined by exposing it to a total of 12 cycles between -195 C and +250 C. Following the cycling activity, measurements were performed again at the test temperatures of -195 C, +21 C, and +250 C.

Patterson, Richard↗
NASA NTRS2010

Modeling of Sonos Memory Cell Erase Cycle

Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile semiconductor memories (NVSMS) have many advantages. These memories are electrically erasable programmable read-only memories (EEPROMs). They utilize low programming voltages, endure extended erase/write cycles, are inherently resistant to radiation, and are compatible with high-density scaled CMOS for low power, portable electronics. The SONOS memory cell erase cycle was investigated using a nonquasi-static (NQS) MOSFET model. The SONOS floating gate charge and voltage, tunneling current, threshold voltage, and drain current were characterized during an erase cycle. Comparisons were made between the model predictions and experimental device data.

Phillips, Thomas A.↗
DOE OSTI2025

Ultranarrow electroluminescence from magnetic excitons in the van der Waals antiferromagnetic semiconductor NiPS 3

Electrically driven light emission from two-dimensional (2D) semiconducting materials has enabled numerous optoelectronic technologies, including light-emitting diodes, solid-state lasers, and single-photon sources for quantum communication. Here we report ultranarrow electroluminescence from the magnetic excitonic state of the van der Waals antiferromagnetic semiconductor NiPS 3 . This electroluminescence is enabled by the fabrication of gate-tunable NiPS 3 devices that remain electrically conductive below the antiferromagnetic ordering temperature of 155 K, ultimately allowing field-effect mobilities of 1.3 cm 2 V –1 s –1 and 4.5 cm 2 V –1 s –1 to be directly measured at room temperature and 7 K, respectively. By applying a high-frequency square wave voltage to the gate electrode of the resulting field-effect transistors, electroluminescence is capacitively induced from the magnetic excitons of NiPS 3 . Due to the coupling of these excitons with the underlying NiPS 3 antiferromagnetic order, the electroluminescence has an ultranarrow linewidth of 1 meV and a high degree of linear polarization (ρ = 0.78). In addition to facilitating fundamental studies of the coupling between spin states and excitons in van der Waals magnetic semiconductors, this work will accelerate the development of emerging 2D opto-spintronic applications.

two-dimensional materials↗
NASA NTRS2002

Modeling of Gate Bias Modulation in Carbon Nanotube Field-Effect-Transistor

The threshold voltages of a carbon-nanotube (CNT) field-effect transistor (FET) are studied. The CNT channel is so thin that there is no voltage drop perpendicular to the gate electrode plane, and this makes the device characteristics quite unique. The relation between the voltage and the electrochemical potentials, and the mass action law for electrons and holes are examined in the context of CNTs, and inversion and accumulation threshold voltages (V(sub Ti), and V(sub Ta)) are derived. V(sub Ti) of the CNTFETs has a much stronger doping dependence than that of the metal-oxide- semiconductor FETs, while V(sub Ta) of both devices depends weakly on doping with the same functional form.

Toshishige, Yamada↗
DOE OSTI2025

Bypassing Fast Time Scales of the Hodgkin-Huxley Neuron Model via a Thresholded Hard Reset

We propose a modification to the Hodgkin-Huxley model to reduce the numerical stiffness of the equations by introducing an explicit voltage threshold. When this threshold is crossed, the voltage and the gating variables are reset to constant values. It is found that, for all of the current stimuli considered, the proposed model accurately reproduces the behavior of the baseline Hodgkin-Huxley model while bypassing the fast dynamics of spiking. Specifically, the model accurately reproduces the spike times and, between spikes, the time courses of the membrane potential and gating variables.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1977

The charge-flow transistor - A new MOS device

A new device, the charge-flow transistor (CFT), has been developed to achieve integrated MOS compatibility in sensor applications, such as gas, humidity, and fire detection, where one is interested in monitoring the transverse resistance of a thin film. The resistive material is incorporated into the gate structure of the CFT in such a way that there is a time delay between the application of the gate-to-source voltage and the appearance of a complete channel. This time delay depends on the resistivity of the thin film. A theory of device operation is presented, together with experimental results on the first CFT's. These results confirm the principles of operation, and demonstrate the utility of the CFT for making fully integrated sensing devices.

Senturia, S. D.↗
NASA NTRS1983

Digital Single-Phase Power-Factor Controller

Digital circuit has faster response to load changes. Digital power-factor controller senses changing motor-load torques by sampling open-circuit voltage across gate-controlled silicon switch. Circuit responds more rapidly to hanging loads than analog power-factor controllers because no low-pass filter is in feedback loop.

Dabney, R. W.↗
NASA NTRS1985

Online Tester for a Symbol Generator

About 95 percent of faults detected. Programable instrument periodically checks for failures in system that generates alphanumerical and other symbol voltages for cathode-ray-tube displays. Symbol-generator tester compares gated test-point voltages with predetermined voltage limits while circuit under test performs commanded operation. A go/no-go indication given, depending on whether test voltage is or is not within its specification. Tester in plug-in modular form, temporarily wired to generator test points, or permanently wired to these points.

Juday, D.↗
NASA NTRS1987

Response of a metal-oxide-semiconductor field-effect transistor to a cosmic-ray ion track

A cosmic-ray ion track passing perpendicularly through the oxide layer of an enhancement-mode metal-oxide-semiconductor field-effect transistor (MOSFET) forms a conducting path, the resistance of which is proportional to the stopping power of the cosmic ion and independent of the cross-sectional area of the ion track. The voltage across the oxide capacitance may drop below the threshold voltage if the gate bias is sufficiently low or if the external resistance in the gate-source circuit is sufficiently high. The first of a pair of MOSFETs forming a flip-flop circuit may thus be turned off, and the second transitor may turn on, providing it has a sufficiently short delay time, thereby completing a single-event upset.

Benumof, Reuben↗
NASA NTRS2009

A Mathematical Model of a Simple Amplifier Using a Ferroelectric Transistor

This paper presents a mathematical model characterizing the behavior of a simple amplifier using a FeFET. The model is based on empirical data and incorporates several variables that affect the output, including frequency, load resistance, and gate-to-source voltage. Since the amplifier is the basis of many circuit configurations, a mathematical model that describes the behavior of a FeFET-based amplifier will help in the integration of FeFETs into many other circuits.

Sayyah, Rana↗
NASA NTRS2010

Modeling a Common-Source Amplifier Using a Ferroelectric Transistor

This paper presents a mathematical model characterizing the behavior of a common-source amplifier using a FeFET. The model is based on empirical data and incorporates several variables that affect the output, including frequency, load resistance, and gate-to-source voltage. Since the common-source amplifier is the most widely used amplifier in MOS technology, understanding and modeling the behavior of the FeFET-based common-source amplifier will help in the integration of FeFETs into many circuits.

Sayyah, Rana↗
NASA NTRS2010

SONOS Nonvolatile Memory Cell Programming Characteristics

Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory is gaining favor over conventional EEPROM FLASH memory technology. This paper characterizes the SONOS write operation using a nonquasi-static MOSFET model. This includes floating gate charge and voltage characteristics as well as tunneling current, voltage threshold and drain current characterization. The characterization of the SONOS memory cell predicted by the model closely agrees with experimental data obtained from actual SONOS memory cells. The tunnel current, drain current, threshold voltage and read drain current all closely agreed with empirical data.

MacLeod, Todd C.↗
DOE OSTI2024

Efficient IGBT switching

Embodiments of the invention provide IGBT circuit modules with increased efficiencies. These efficiencies can be realized in a number of ways. In some embodiments, the gate resistance and/or voltage can be minimized. In some embodiments, the IGBT circuit module can be switched using an isolated receiver such as a fiber optic receiver. In some embodiments, a single driver can drive a single IGBT. And in some embodiments, a current bypass circuit can be included. Various other embodiments of the invention are disclosed.

Ziemba, Timothy↗