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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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The engineering development of a solid state transmitter amplifier operating in the 20 GHz frequency band. The development effort involved a variety of disciplines including IMPATT device development, circulator design, simple and multiple diode circuits designs, and amplifier integration and test.
Winner-take-all circuit selects best-match stored pattern. Prototype cascadable very-large-scale integrated (VLSI) circuit chips built and tested to demonstrate concept of electronic associative pattern recognition. Based on low-power, sub-threshold analog complementary oxide/semiconductor (CMOS) VLSI circuitry, each chip can store 128 sets (vectors) of 16 analog values (vector components), vectors representing known patterns as diverse as spectra, histograms, graphs, or brightnesses of pixels in images. Chips exploit parallel nature of vector quantization architecture to implement highly parallel processing in relatively simple computational cells. Through collective action, cells classify input pattern in fraction of microsecond while consuming power of few microwatts.
Electrical characterization tests were performed on two different manufactured types of integrated circuits. The devices were subjected to functional and AC and DC parametric tests at ambient temperatures of -55 C, -20 C, 25 C, 85 C, and 125 C. The data were analyzed and tabulated to show the effect of operating conditions on performance and to indicate parameter deviations among devices in each group. Accuracy was given precedence over test time efficiency where practical, and tests were designed to measure worst case performance.
As microelectronics is scaled into the deep sub-micron regime, space and aerospace users of advanced technology CMOS are reassessing how scaling effects impact long-term product reliability. The effects of electromigration (EM), time-dependent-dielectric-breakdown (TDDB) and hot carrier degradation (HCI and NBTI) wearout mechanisms on scaled technologies and product reliability are investigated, accelerated stress testing across several technology nodes is performed, and FA is conducted to confirm the failure mechanism(s).
Report details the test and inspection procedures for the mass production of high reliability integrated circuits. It covers configuration control, basic fundamentals of quality control, control charts, wafer process evaluation, general process evaluation, evaluation score system, and diffusion evaluation.
The importance of Cosmic Rays on the performance of integrated circuits (IC's) in a space environment is evident in the upset rate of the Tracking and Data Relay Satellite (TDRS) launched in Apr. 1983. This satellite experiences a single-event-upset (SEU) per day which must be corrected from the ground. Such experience caused a redesign of the Galileo spacecraft with SEU resistant IC's. The solution to the SEU problem continues to be important as the complexity of spacecraft grows, the feature size of IC's decreases, and as space systems are designed with circuits fabricated at non-radiation hardened foundries. This paper describes an approach for verifying the susceptibility of CMOS latches to heavy-ion induced state changes. The approach utilizes alpha particles to induce the upsets in test circuits. These test circuits are standard cells that have offset voltages which sensitize the circuits to upsets. These results are then used to calculate the upsetability at operating voltages. In this study results are presented for the alpha particle upset of a six-transistor static random access memory (SRAM) cell. Then a methodology is described for the analysis of a standard-cell inverter latch.
This paper describes initial development and testing of a novel high temperature capacitive pressure sensor system. The pressure sensor system consists of two 4H-SiC 11-stage ring oscillators and a SiCN capacitive pressure sensor. One oscillator has the capacitive pressure sensor fixed at one node in its feedback loop and varies as a function of pressure and temperature while the other provides a pressure-independent reference frequency which can be used to temperature compensate the output of the first oscillator. A two-day repeatability test was performed up to 500C on the oscillators and the oscillator fundamental frequency changed by only 1. The SiCN capacitive pressure sensor was characterized at room temperature from 0 to 300 psi. The sensor had an initial capacitance of 3.76 pF at 0 psi and 1.75 pF at 300 psi corresponding to a 54 change in capacitance. The integrated pressure sensor system was characterized from 0 to 300 psi in steps of 50 psi over a temperature range of 25 to 500C. The pressure sensor system sensitivity was 0.113 kHzpsi at 25C and 0.026 kHzpsi at 500C.
A microwave integrated circuit active receiver is built and tested at 19-25 GHz. The receiver consists of a planar CPW-fed double folded-slot antenna coupled to a six-stage MESFET (metal semiconductor field effect transistors) amplifier and followed by a planar Schottky-diode detector. The folded-slot antenna on a GaAs half-space results in a wide frequency bandwidth suitable for MMIC amplifiers. The measured system performance show a video responsivity close to 1 GV/W at 20 GHz with a 3-dB bandwidth of 1500 MHz. A novel method which uses the planar video detector after the amplifier stages as an RF (radio frequency) mixer is used to measure the noise-figure of the direct detection radiometer. The system noise figure is 4.8 dB at 22 GHz. The radiometer sensitivity to a hot/cold load is 3.8 mu V/K. The measured antenna patterns show a 90% Gaussicity at 20-22 GHz. The active MIC receiver can be integrated monolithically for low-cost applications and is well suited for millimeter-wave linear imaging arrays.
Method for design of accelerated tests of electromigration (as in microscopic conductors in integrated circuits) based partly on simplified mathematical model of electromigration and partly on error analysis. Objective to determine quickly operating life of tested components under normal operating conditions by extrapolation from lifetime measurements at operating stresses greater than normal. Involves compromise between reducing testing time by increasing stresses and reducing uncertainty in extrapolated lifetime by decreasing stresses.
Spacecraft thermal control is accomplished for many components through use of multilayer insulation systems, electrical heaters, and radiator systems. The heaters are commanded to maintain component temperatures within design specifications. The programmable heater control circuit (PHCC) was designed to obtain an effective and efficient means of spacecraft thermal control. The hybrid circuit provides use of control instrumentation as temperature data, available to the spacecraft central data system, reprogramming capability of the local microprocessor during the spacecraft's mission, and the elimination of significant spacecraft wiring. The hybrid integrated circuit has a temperature sensing and conditioning circuit, a microprocessor, and a heater power and control circuit. The device is miniature and housed in a volume which allows physical integration with the component to be controlled. Applications might include alternate battery-powered logic-circuit configurations. A prototype unit with appropriate physical and functional interfaces was procured for testing. The physical functionality and the feasibility of fabrication of the hybrid integrated circuit were successfully verified. The remaining work to develop a flight-qualified device includes fabrication and testing of a Mil-certified part. An option for completing the PHCC flight qualification testing is to enter into a joint venture with industry.
The GEO-CAPE mission described in NASA's Earth Science and Applications Decadal Survey requires high spatial, temporal, and spectral resolution measurements to monitor and characterize the rapidly changing chemistry of the troposphere over North and South Americas. High-frame-rate focal plane arrays (FPAs) with many pixels are needed to enable such measurements. A high-throughput digital detector readout integrated circuit (ROIC) that meets the GEO-CAPE FPA needs has been developed, fabricated, and tested. The ROIC is based on an innovative charge integrating, fast, high-precision analog-to-digital circuit that is built into each pixel. The 128×128-pixel ROIC digitizes all 16,384 pixels simultaneously at frame rates up to 16 kHz to provide a completely digital output on a single integrated circuit at an unprecedented rate of 262 million pixels per second. The approach eliminates the need for off focal plane electronics, greatly reducing volume, mass, and power compared to conventional FPA implementations. A focal plane based on this ROIC will require less than 2 W of power on a 1×1-cm integrated circuit. The ROIC is fabricated of silicon using CMOS technology. It is designed to be indium bump bonded to a variety of detector materials including silicon PIN diodes, indium antimonide (InSb), indium gallium arsenide (In- GaAs), and mercury cadmium telluride (HgCdTe) detector arrays to provide coverage over a broad spectral range in the infrared, visible, and ultraviolet spectral ranges.
Guidelines for the design, development, and fabrication of electronic components and circuits for use in spacecraft construction are presented. The subjects discussed involve quality control procedures and test methodology for the following subjects: (1) monolithic integrated circuits, (2) hybrid integrated circuits, (3) transistors, (4) diodes, (5) tantalum capacitors, (6) electromechanical relays, (7) switches and circuit breakers, and (8) electronic packaging.
Topics covered include: A Multifunctional Space Environment Simulation Facility for Accelerated Spacecraft Materials Testing; Exposure of Spacecraft Surface Coatings in a Simulated GEO Radiation Environment; Gravity-Offloading System for Large-Displacement Ground Testing of Spacecraft Mechanisms; Microscopic Shutters Controlled by cRIO in Sounding Rocket; Application of a Physics-Based Stabilization Criterion to Flight System Thermal Testing; Upgrade of a Thermal Vacuum Chamber for 20 Kelvin Operations; A New Approach to Improve the Uniformity of Solar Simulator; A Perfect Space Simulation Storm; A Planetary Environmental Simulator/Test Facility; Collimation Mirror Segment Refurbishment inside ESA s Large Space; Space Simulation of the CBERS 3 and 4 Satellite Thermal Model in the New Brazilian 6x8m Thermal Vacuum Chamber; The Certification of Environmental Chambers for Testing Flight Hardware; Space Systems Environmental Test Facility Database (SSETFD), Website Development Status; Wallops Flight Facility: Current and Future Test Capabilities for Suborbital and Orbital Projects; Force Limited Vibration Testing of JWST NIRSpec Instrument Using Strain Gages; Investigation of Acoustic Field Uniformity in Direct Field Acoustic Testing; Recent Developments in Direct Field Acoustic Testing; Assembly, Integration and Test Centre in Malaysia: Integration between Building Construction Works and Equipment Installation; Complex Ground Support Equipment for Satellite Thermal Vacuum Test; Effect of Charging Electron Exposure on 1064nm Transmission through Bare Sapphire Optics and SiO2 over HfO2 AR-Coated Sapphire Optics; Environmental Testing Activities and Capabilities for Turkish Space Industry; Integrated Circuit Reliability Simulation in Space Environments; Micrometeoroid Impacts and Optical Scatter in Space Environment; Overcoming Unintended Consequences of Ambient Pressure Thermal Cycling Environmental Tests; Performance and Functionality Improvements to Next Generation Thermal Vacuum Control System; Robotic Lunar Lander Development Project: Three-Dimensional Dynamic Stability Testing and Analysis; Thermal Physical Properties of Thermal Coatings for Spacecraft in Wide Range of Environmental Conditions: Experimental and Theoretical Study; Molecular Contamination Generated in Thermal Vacuum Chambers; Preventing Cross Contamination of Hardware in Thermal Vacuum Chambers; Towards Validation of Particulate Transport Code; Updated Trends in Materials' Outgassing Technology; Electrical Power and Data Acquisition Setup for the CBER 3 and 4 Satellite TBT; Method of Obtaining High Resolution Intrinsic Wire Boom Damping Parameters for Multi-Body Dynamics Simulations; and Thermal Vacuum Testing with Scalable Software Developed In-House.
Precise test pulse with stable duration and amplitude needed for calibration of test equipment. Precise-test-pulse generator provides such waveform and has additional desirable features. Circuit produces single test pulses of stable duration and amplitude. Made of commercially available integrated circuits and discrete components.
Adaptation of models for minority carrier devices, and applicability in computer design evaluation studies of integrated circuits
The automatic picture transmission digital scan converter is used at ground stations to convert signals received from scanning radiometers to data compatible with ground equipment designed to receive signals from vidicons aboard operational meteorological satellites. Information necessary to understand the circuit theory, functional operation, general construction and calibration of the converter is provided. Brief and detailed descriptions of each of the individual circuits are included, accompanied by a schematic diagram contained at the end of each circuit description. Listings of integral parts and testing equipment required as well as an overall wiring diagram are included. This unit will enable the user to readily accept and process weather photographs from the operational meteorological satellites.
Report describes experimental study of use of microelectronic advanced laser scanner (MEALS) to cause single-event upsets (SEUs) in integrated logic circuits. Basic concepts of SEU testing by use of MEALS described in "Laser Scanner Tests for Single-Event Upsets" (NPO-18216), "Single-Event-Upset Laser Scanner With Optical Bias" (NPO-18217), and "More About Laser Scanner Tests for Single-Event Upsets" (NPO-18494). Study part of continuing effort to study SEU effects of ionizing radiation on such circuits and to use MEALS as relatively inexpensive SEU-prescreening laboratory apparatus serving as alternative to heavy-ion acclerator.
This article summarizes the design concepts applied in the development of and advanced Ka-band (34.4 GHz/32 GHz) transponder breadboard for the next generation of space communications systems applications. The selected architecture upgrades the X-band (7.2 GHz/8.4 GHz) deep-space transponder (DST) to provide Da-band up/Ka- and X-band down capability. The Ka-band transponder breadboard incorporates several state-of-the-art components, including sampling mixers, a Ka-band dielectric resonator oscillator, and microwave monolithic integrated circuits (MMICs). The MMICs that were tested in the breadboard include upconverters, downconverters, automatic gain control circuits, mixers, phase modulators, and amplifiers. The measured receiver dynamic range, tracking range, acquisition rate, static phase error, and phase jitter characteristics of the Ka-band breadboard interfaced to the advanced engineering model X-band DST are in good agreement with the expected performance. The results show a receiver tracking threshold of -149 dBm with a dynamic range of 80 dB and a downlink phase jitter of 7 deg rms. The analytical results of phase noise and Allan standard deviation are in good agreement with the experimental results.