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At least 145 records · Page 8

Ultrafast Activation and Tuning of Topological Textures in Ferroelectric Nanostructures

Polar topological textures are recently discovered in ultra–thin ferroelectrics, including stripe, labyrinth, or bubble states. Enabling to shape on–demand, these topologies herein can provide an original platform for potential applications. Here, using first–principle–based calculations, it is shown that THz electric field pulses are an efficient means for generating a plethora of topological states in ultrathin films made by a prototypical ferroelectric system, depending on the characteristics of these pulses and films. Consequently, these ultrafast electrical pulses in ultra–thin ferroelectrics offer key ingredients for mimicking neuronal and synaptic behaviors, including all–optical devices, and open a new avenue for topological objects to neuromorphic systems.

36 MATERIALS SCIENCE↗

Quantum graph models for transport in filamentary switching

The formation of metallic nanofilaments bridging two electrodes across an insulator is a mechanism for resistive switching. Examples of such phenomena include atomic synapses, which constitute a distinct class of memristive devices the behavior of which is closely tied to the properties of the filament. Until recently, experimental investigation of the low-temperature regime and quantum transport effects has been limited. However, with growing interest in understanding the true impacts of the filament on device conductance, comprehending quantum effects has become crucial for quantum neuromorphic hardware. Here, we discuss quantum transport resulting from filamentary switching in a narrow region where the continuous approximation of the contact is not valid, and only a few atoms are involved. In this scenario, the filament can be represented by a graph depicting the adjacency of atoms and the overlap between atomic orbitals. Using the theory of quantum graphs with locally diffusive node scattering, we calculate the scattering amplitude of charge carriers on this graph and explore the interplay between filamentary formation and quantum transport effects.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Enhanced read resolution in reconfigurable memristive synapses for Spiking Neural Networks

Abstract The synapse is a key element circuit in any memristor-based neuromorphic computing system. A memristor is a two-terminal analog memory device. Memristive synapses suffer from various challenges including high voltage, SET or RESET failure, and READ margin issues that can degrade the distinguishability of stored weights. Enhancing READ resolution is very important to improving the reliability of memristive synapses. Usually, the READ resolution is very small for a memristive synapse with a 4-bit data precision. This work considers a step-by-step analysis to enhance the READ current resolution or the read current difference between two resistance levels for a current-controlled memristor-based synapse. An empirical model is used to characterize the $${\hbox {HfO}}_{2}$$ HfO 2 based memristive device. $$1\textrm{st}$$ 1 st and $$2\textrm{nd}$$ 2 nd stage device of our proposed synapse design can be scaled to enhance the READ current margin up to $$\sim$$ ∼ 4.3 $$\times$$ × and $$\sim$$ ∼ 21%, respectively. Moreover, READ current resolution can be enhanced with run-time adaptation techniques such as READ voltage scaling and body biasing. The READ voltage scaling and body biasing can improve the READ current resolution by about 46% and 15%, respectively. TENNLab’s neuromorphic computing framework is leveraged to evaluate the effect of READ current resolution on classification, control, and reservoir computing applications. Higher READ current resolution shows better accuracy than lower resolution even when facing different levels of read noise.

97 MATHEMATICS AND COMPUTING↗

An interface-controlled Mott memristor in α -RuCl 3

Memristor devices have history-dependent charge transport properties that are ideal for neuromorphic computing applications. We reveal a memristor material and mechanism in the layered Mott insulator α-RuCl 3 . The pinched hysteresis loops and S-shaped negative differential resistance in bulk crystals verify memristor behavior and are attributed to a nonlinear coupling between charge injection over a Schottky barrier at the electrical contacts and concurrent Joule heating. Direct simulations of this coupling can reproduce the device characteristics.

Physics↗

Uncontrolled Learning: Codesign of Neuromorphic Hardware Topology for Neuromorphic Algorithms

Neuromorphic computing has the potential to revolutionize future technologies and our understanding of intelligence, yet it remains challenging to realize in practice. The learning-from-mistakes algorithm, inspired by the brain's simple learning rules of inhibition and pruning, is one of the few brain-like training methods. This algorithm is implemented in neuromorphic memristive hardware through a codesign process that evaluates essential hardware trade-offs. While the algorithm effectively trains small networks as binary classifiers and perceptrons, performance declines significantly with increasing network size unless the hardware is tailored to the algorithm. This work investigates the trade-offs between depth, controllability, and capacity—the number of learnable patterns—in neuromorphic hardware. This highlights the importance of topology and governing equations, providing theoretical tools to evaluate a device's computational capacity based on its measurements and circuit structure. The findings show that breaking neural network symmetry enhances both controllability and capacity. Additionally, by pruning the circuit, neuromorphic algorithms in all-memristive circuits can utilize stochastic resources to create local contrasts in network weights. Through combined experimental and simulation efforts, the parameters are identified that enable networks to exhibit emergent intelligence from simple rules, advancing the potential of neuromorphic computing.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Multiparametric AFM Insights into Electron Transport Mechanisms in Biomemristors

Biomemristors have attracted significant attention due to their applications in biodegradable and flexible electronic devices, and their prospective functions in information storage, neural synapses, and neuromorphic computation. Hence, understanding biomaterials' resistive switching (RS) mechanism is essential to design novel biomemristors with enhanced performance. In the last decade, various atomic force microscopy (AFM) modes, such as Kelvin probe force microscopy (KPFM) and conductive atomic force microscopy (cAFM), in situ/operando visualize the electron transport behaviors within biomemristors at the nanoscale. This review provides a comprehensive discussion of multiparametric AFM techniques to characterize biomemristors and inspire new ideas in developing next-generation consumer electronics. We also summarize the progress of revealing the internal mechanism of biomemristors with functional AFM to visualize and understand the switching behavior. Finally, the opportunities and challenges of further utilizing multiparametric AFM to explore the electron transport mechanisms in biomemristors are presented.

Shi, Chenyang↗

Three-Dimensional Integration of Functional Oxides and Crystalline Silicon for Optical Neuromorphic Computing Using Nanometer-Scale Oxygen Scavenging Barriers

Dating to the first reports of epitaxial oxide deposition on Si(001), the integration of complex oxides on silicon has been a fast-moving area of research, where fundamental materials physics is intimately connected to tremendous technological promise in such areas as integrated electronics, optical neuromorphic and quantum computing, and sensing, to name a few. Despite their great promise, devices relying on the co-integration of silicon and epitaxial perovskites are typically limited to basic, planar geometries due to practical issues with their fabrication. In this paper, we overcome these long-standing challenges by developing a method to produce high-quality Si(001)/TMO/Si(001)/TMO heterostructures without wafer bonding, resulting in the straightforward three-dimensional integration of functional complex oxides and active Si(001) layers into a technologically relevant platform that is needed for on-chip hardware implementations of neuromorphic computing based on optical signals. We present detailed structural and chemical characterization of our heterostructures and discuss generalized design rules for their fabrication. Our results exponentially expand the universe of practically achievable TMO-based integrated devices and push this promising class of materials closer to realizing their full technological potential.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

Probing the Effects of the First Atomic Layer on the Dynamic Behavior of Sub-2 nm MgO/Al 2 O 3 Memristors

As electronic devices continue to scale down from the current sub-5 nm range, atomic-scale control of defects becomes increasingly crucial to suppressing their impact on the physical properties of the devices. Memristors present an excellent example as a nonlinear and dynamic device with high speed and endurance required for electronic applications ranging from neuromorphic computing to nonvolatile memories. Herein we investigate the impact of atomic defects in sub-2 nm thick MgO/Al 2 O 3 atomic layer stack (ALS) memristors that use an M1 (switching layer)/M2 (oxygen vacancy reservoir layer) bilayer structure grown using in vacuo atomic layer deposition (iALD). Intriguingly, we revealed a direct correlation of the atomic defects in the M2 layer with the memristor dynamic behavior using a combined analysis of in situ scanning tunneling spectroscopy (iSTS) on the M2 layer and ex situ characterization on the memristors. Specifically, incomplete coverage of the 1st ALD atomic layer of M2 on the electrode yields defects at the M2/electrode interface. Despite the monotonic increase of ALD coverage, by almost three-fold from ~30% to >90%, at completion of the M2 layer of ~ 0.7 nm in thickness, the impact of the defects on the M2/electrode interface has been found detrimental to both memristor switching speed and endurance. Guided by atomistic simulation, we addressed the issue of interface defects via tuning of the Al surface hydroxylation to increase the first atomic layer ALD coverage to ~75%, leading to improved memristor switching speed and endurance by several orders of magnitude. In conclusion, these findings shed light on the correlation between the atomic defects and the dynamic behavior of sub-2 nm memristors and the importance of minimizing the atomic defects in memristors for future electronic applications.

Atomic Layer Deposition↗

Probabilistic Neural Computing with Stochastic Devices

Abstract The brain has effectively proven a powerful inspiration for the development of computing architectures in which processing is tightly integrated with memory, communication is event‐driven, and analog computation can be performed at scale. These neuromorphic systems increasingly show an ability to improve the efficiency and speed of scientific computing and artificial intelligence applications. Herein, it is proposed that the brain's ubiquitous stochasticity represents an additional source of inspiration for expanding the reach of neuromorphic computing to probabilistic applications. To date, many efforts exploring probabilistic computing have focused primarily on one scale of the microelectronics stack, such as implementing probabilistic algorithms on deterministic hardware or developing probabilistic devices and circuits with the expectation that they will be leveraged by eventual probabilistic architectures. A co‐design vision is described by which large numbers of devices, such as magnetic tunnel junctions and tunnel diodes, can be operated in a stochastic regime and incorporated into a scalable neuromorphic architecture that can impact a number of probabilistic computing applications, such as Monte Carlo simulations and Bayesian neural networks. Finally, a framework is presented to categorize increasingly advanced hardware‐based probabilistic computing technologies.

Misra, Shashank↗

Self‐Strain Suppression of the Metal‐to‐Insulator Transition in Phase‐Change Oxide Devices

Strongly correlated materials exhibiting phase transitions which can be controlled through external stimuli, such as electric fields, are promising for future computing technologies beyond conventional semiconductor transistors. Devices that take advantage of structural phase transitions have inherent built‐in memory, reminiscent of synapses and neurons, and are thus natural candidates for neuromorphic computing. Of particular interest are phase‐change oxides, which allow for control over the metal‐to‐insulator transition. Here, X‐ray nano‐diffraction structural imaging of micro‐devices fabricated with the archetypal phase‐change material vanadium sesquioxide (V 2 O 3 ) is reported. The devices contain a Ga ion‐irradiated region where the metal‐to‐insulator transition critical temperature is lowered, a useful feature for controlling neuron‐like spiking behavior. Results show that strain, induced by crystal lattice mismatch between the pristine and irradiated material, leads to a suppression of the metal‐to‐insulator‐transition. Suppression occurs within the irradiated region or along its edges, depending on the defect‐distribution and the size of the region. The observed self‐straining effect can extend to other phase‐change oxides and dominate as device dimensions are reduced and become too small to dissipate strain within the irradiated region. The findings are important for phase engineering in phase‐change devices and highlight the necessity to study phase transitions at the nanoscale.

77 NANOSCIENCE AND NANOTECHNOLOGY↗

Tunable Interfacial to Filamentary Resistive Switching Mechanism in Room-Temperature-Grown Amorphous YBa 2 Cu 3 O x with Excess Cu Addition

Resistive switching technologies have the potential not only to create large efficiency gains in computer memory but also to revolutionize emerging fields such as neuromorphic computing. In this paper, we report on novel resistive switching behavior in devices made from room-temperature-grown Cu-rich amorphous YBa 2 Cu 3 O x (YBCO) films, a material otherwise well-known as a high-temperature superconductor. In Nb:STO substrate/amorphous YBCO film (≈200 nm)/metallic Cu (15 nm)/metallic Pt (15 nm) devices, we demonstrate that the resistive switching can be tuned between mechanisms involving extended areas of the YBCO/electrode interface and a single-point filamentary mechanism simply by changing the Cu content of the deposition target and hence in the films. Changing the Cu content can also be used to optimize the properties of the devices further, with devices with an added 15 mol % of Cu in YBCO initially providing an on/off ratio >100, switching endurance potential >6500 cycles, and state retention >2 × 10 4 s, all at low switching fields of 0.3 MV/cm. The amalgam of promising resistive switching properties, fast growth (150 nm/min) at room temperature, and tuneability of the switching mechanism indicates the strong potential of this proof-of-concept amorphous system for future memory applications.

Cu↗

Mixed-dimensional stackable electronics enabled by freestanding 2D/3D materials

2D material-based devices have received great deal of attention as they can be easily stacked to obtain multifunctionality. With their ultrathin thicknesses, such multifunctioning devices become so flexible and conformal that they can be placed onto any 3D featured surfaces. However, 2D heterostructures are typically demonstrated as stacked flakes where single or few devices can be fabricated due to lack of strategies for layer-by-layer stacking of 2D materials at the wafer scale. In this talk, I will discuss about our unique strategy to isolate wafer-scale 2D materials into monolayers and stack them into a heterostructures by using a layer-resolved splitting (LRS) technique. This technique enables my group at MIT to explore unprecedented wafer-scale 2D heterodevices including integrated photonics, 3D neuromorphic computing, and microLEDs, which will be introduced in my talk. While 2D heterostructures promise interesting futuristic devices, the performance of 2D material-based devices is substantially inferior to that of conventional 3D semiconductor materials. However, 3D materials exist as their bulk form, thus it is challenging to stack them together for heterostructures. Obviously, conformal coating of such single-crystalline bulks on 3D features is impossible. My group at MIT has recently invented a 2D materials-based layer transfer (2DLT) technique that can produce single-crystalline freestanding membranes from any compound materials with their excellent semiconducting performance. This technique is based on remote epitaxy of single-crystalline films on graphene followed by peeling from graphene. Stacking of freestanding 3D material membranes will enable unprecedented 3D heterostructures whose performance is expected to be superior to that of 2D heterostructures. I will talk about our group’s effort to apply single-crystalline freestanding membranes for flexible, conformal electronics as well as for 3D heterostructures. Finally, I will conclude my talk by discussing perspectives of coupling 2D-3D freestanding membranes for 2D-3D mixed heterostructured devices that can be enabled by our LRS and 2DLT techniques.

Kim, Jeehwan↗

AI-enhanced Codesign for Next-Generation Neuromorphic Circuits and Systems

This report details work that was completed to address the Fiscal Year 2022 Advanced Science and Technology (AS&T) Laboratory Directed Research and Development (LDRD) call for “AI-enhanced Co-Design of Next Generation Microelectronics.” This project required concurrent contributions from the fields of 1) materials science, 2) devices and circuits, 3) physics of computing, and 4) algorithms and system architectures. During this project, we developed AI-enhanced circuit design methods that relied on reinforcement learning and evolutionary algorithms. The AI-enhanced design methods were tested on neuromorphic circuit design problems that have real-world applications related to Sandia’s mission needs. The developed methods enable the design of circuits, including circuits that are built from emerging devices, and they were also extended to enable novel device discovery. We expect that these AI-enhanced design methods will accelerate progress towards developing next-generation, high-performance neuromorphic computing systems.

42 ENGINEERING↗

Neuromorphic heat transport effects in a molecular junction

Understanding energy transport at the nanoscale is an open and fundamental challenge in the molecular sciences with direct implications for the design of new electronics, computing devices, and materials. While nanoscale energy transport under steady-state conditions has been studied extensively, there is much less known about energy transport under time-dependent driving forces, particularly in the far-from-equilibrium regime. In this work, we use nonequilibrium molecular dynamics simulations and stochastic thermodynamics to investigate energy transport in a well-studied nanoscale system—a molecular junction—subjected to a time-periodic temperature gradient. The primary observation is that molecular junctions can exhibit heat transport hysteresis, a phenomenon in which the heat flux through a system depends not only on the instantaneous value of a time-dependent temperature bias but also on the temporal history of that bias. The presented findings illustrate that molecular junctions can exhibit the specific memory effect—heat transport hysteresis—that is essential for the design of thermal neuromorphic computers. This work elucidates a potential pathway toward the realization of such devices.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Magnetic Solitons and Thickness‐Dependent Magnetization Reversal in Interconnected Helical Nanowire Arrays

By expanding magnetic nanostructures into the third dimension, it is possible to introduce new interactions and realize new forms of magnetic textures and emergent phenomena. Consequently, this unlocks new opportunities for applications in data storage, unconventional computing and sensing by utilizing 3D devices with enhanced functionalities. Connected magnetic nanowires offer a unique platform for applications such as neuromorphic computing due to their tunability and the presence of multiple transport pathways. However to realize this promise, it is necessary to further our understanding of how to locally control the magnetization in 3D, nanowire-based geometries. In this work we show the formation of magnetic domain walls, vortices, anti-vortices, and linked vortex-anti-vortex pairs in interconnected helical nanowire arrays. We show how wire diameter and 3D geometric design can control the states that form and reveal the magnetization reversal mechanism. Hence, we demonstrate this to be a highly tunable system, where the magnetization can be readily reconfigured by an external magnetic field.

3D Nanomagnetism↗

The organic redox transistor for neuromorphic computing

Inspired by the in-memory computing architectures of biological systems, neuromorphic computing using crossbar arrays of artificial synapses based on non-volatile memory (NVM) devices with variable conductances has emerged as a new paradigm to enable massively parallel and ultra-low power computing hardware for data centric applications. Although inference has been demonstrated successfully using crossbars based on a variety of NMV technologies, efficient learning and scaling to large arrays (>10 6 elements) remains a challenge due to the synaptic elements' non-ideal electrical characteristics which degrades ANN accuracy. A further challenge is that in the conductive state memristors draw large currents >μA resulting in significant voltage drops in the interconnect wires and increased probability of failure in scaled arrays. We suggest the organic polymer redox transistor (RT) is an alternate approach that could solve many of these challenges, enabling both inference and parallel outer product updates, as recently demonstrated by Fuller et al. An RT consists of redox-active channel and gate electrodes in contact with a liquid or solid electrolyte. lon insertion through the electrolyte controls the channel electronic conductivity, while electron transfer through an external circuit maintains overall charge neutrality. Unlike a rechargeable battery, in the RT the voltage built-up across the electrolyte is kept to a minimum (typically <100 mV) by using the same material for the gate and channel. Elimination of the voltage offset simplifies integration of the RT into programmable arrays by enabling the use of various selectors. RTs based on inorganic and organic materials have been recently demonstrated with conductance tuning occurring at potentials of just a few mV and hundreds to thousands of linearly and symmetrically programmable conductance states, enabling near ideal accuracy in neural network simulations. Introduced in the 1980's, redox transistors with metallic gate electrodes and organic channel materials, also known as organic electrochemical transistors (OECTs), have been explored for a variety of applications such as chem- and bio-sensing, neural interfaces, and low cost printed circuits. A typical channel material for OECTs is the conducting polymer poly(3,4-ethylenedioxythiophene) doped with poly(styrene sulfonate) (PEDOT:PSS). PEDOT is a p-type semiconducting polymer with mobile positively charged polarons that hop chain-to-chain.

Talin, Albert Alec↗

Intrinsic synaptic plasticity of ferroelectric field effect transistors for online learning

Nanoelectronic devices emulating neuro-synaptic functionalities through their intrinsic physics at low operating energies is imperative toward the realization of brain-like neuromorphic computers. In this work, we leverage the non-linear voltage dependent partial polarization switching of a ferroelectric field effect transistor to mimic plasticity characteristics of biological synapses. Here, we provide experimental measurements of the synaptic characteristics for a 28nm high-k metal gate technology based device and develop an experimentally calibrated device model for large-scale system performance prediction. Decoupled read-write paths, ultra-low programming energies and the possibility of arranging such devices in a cross-point architecture demonstrate the synaptic efficacy of the device. Our hardware-algorithm co-design analysis reveals that the intrinsic plasticity of the ferroelectric devices has potential to enable unsupervised local learning in edge devices with limited training data

42 ENGINEERING↗

PowerMappeR: Power-Optimized Mapping of SNNs onto ReRAM Crossbars coupled via Packet-Switched NoCs

Many recent efforts in developing hardware-accelerated spiking neural networks (SNNs) are characterized by deep co-design between algorithms, architectures, and devices. Architectural advances overcome device constraints by coupling together many small resistive-RAM (ReRAM) crossbars via a network-on-chip (NoC) for neuromorphic component operation. Concurrently, improved SNN training methods increase accuracy and structural sparsity in networks despite growing problem sizes. Finally, compilers leverage these attributes to minimize area and inter-crossbar communication while mapping large SNNs to sophisticated architectures. However, for compiler-driven co-design to realize increasingly complex and profitable optimizations, a compile-time view of power consumption is critical. We present PowerMappeR to express and optimize over mapping-, architecture-, and device-specific power consumption information. By modeling the dynamic power of well-established components, we develop an integer linear programming (ILP)-based, encoding-agnostic, parametric power estimation model. Using this model, we demonstrate practical improvements in area and inter-crossbar communication by 0%–9.5% and 1.4%–5.1%, respectively. We also limit hotspot formation during optimization, achieving comparable or better results in targeted metrics with up to 96.4%–97.1% restriction of hotspot magnitude. Finally, we introduce profile-guided formulations to reduce worst-case and expected-case hotspot magnitude by 40.7%–69.5% and 40.6%–56.3%, respectively. Optimizing worst-case hotspot magnitude incidentally improves expected-case magnitude by 10.85%–33.45%. Reciprocally, optimizing expected-case magnitude incidentally improves worst-case magnitude by 4.33%–39.87%. Validation against hardware simulators confirms that PowerMappeR can decrease dynamic power consumption by 12.6%–27.3%.

Pohl, Devin [ORNL] (ORCID:0009000040149027)↗