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All sourcesNASA NTRSDOE OSTI
NASA NTRSDate not supplied

Neurovascular Responses to Simulated Deep Space Radiation in a Human Organ-on-a-Chip Model

A major health risk for human deep space exploration is central nervous system (CNS) damage by galactic cosmic ray radiation. Simulated galactic cosmic rays or their components, especially the high-linear energy transfer (LET) particles such as 56Fe ions, have been shown to cause CNS damage, neuroinflammation and cognitive dysfunction in rodent models, but their effects on human CNS remain to be investigated. CNS damage from any insult, including ionizing radiation, is partially mediated by the blood-brain barrier (BBB), which regulates interactions between CNS and the rest of the body. The main cellular regulators of BBB permeability are astrocytes, which also modulate neuroinflammation. However, there have been few studies on BBB and astrocyte functions in regulating CNS responses, especially in human tissue analogs. Therefore, we utilized a high-throughput 3D organ-on-a-chip system, seeded with human induced pluripotent stem cell-derived astrocytes and brain endothelial cells, or brain endothelial cells alone, to study human neurovascular responses to simulated deep space radiation. We investigated the permeability and morphology of vascular structures formed by endothelial cells, as well as oxidative stress and secreted cytokines and chemokine levels over 1-7 days after irradiation with 0.25 – 0.5 Gy 5-ion simplified simulated galactic cosmic rays or 0.3 – 0.8 Gy high-LET 600 MeV/n 56Fe particles, and compared the outcomes to low-LET X-ray irradiation. We observed that simulated deep space radiation caused delayed astrocyte activation in a pattern resembling CNS responses to brain injury, caused oxidative stress and the production of inflammatory cytokines, and compromised BBB integrity by damaging tight junctions, thus increasing vascular permeability. Furthermore, our results indicate that astrocytes have a dual role in regulating radiation responses: they exacerbate blood-brain barrier permeability early after irradiation, followed by switching to a more protective scar-like phenotype by reducing oxidative stress and pro-inflammatory cytokine and chemokine secretion. In a follow-up study using the same platform, we investigated the dose-rate effects of ionizing radiation, by exposing our model to chronic, low dose-rate, gamma radiation. Our model was significantly improved by adding additional cell types composing the BBB, modelling immune cell infiltration into the brain, and studying the effect of an antioxidant, to measure more complex outcomes and model more closely the effect of deep space radiation on the human BBB. In summary, our results present a human neurovascular model for space radiation studies and potential future automated payload adaptation, and suggest astrocyte regulatory mechanisms as targets for countermeasures to mitigate human neurovascular impairments during deep space exploration.

Ionizing radiation↗
NASA NTRSDate not supplied

Deep Space Radiation Affects Neurovascular Functions in Human Organ-on-a-Chip Models

A major health risk for human deep space exploration is central nervous system (CNS) damage by galactic cosmic ray radiation. Simulated galactic cosmic rays or their components, especially the high- linear energy transfer (LET) particles such as 56 Fe ions, cause CNS damage, neuroinflammation and cognitive dysfunction in rodent models, but their effects on human CNS remain to be investigated. CNS damage from any insult, including ionizing radiation, is partially mediated by the blood-brain barrier (BBB), which regulates the interactions between CNS and the rest of the body. The main cellular regulators of BBB permeability are astrocytes, which also modulate neuronal health and neuroinflammation. However, there have been few studies on BBB and astrocyte functions in regulating CNS responses, especially in human tissue/organ analogs. Therefore, we utilized a high-throughput human 3D organ-on-a-chip system, seeded with induced pluripotent stem cell-derived endothelial cells, astrocytes and neurons, to study human neurovascular responses to simulated deep space radiation. We investigated BBB permeability, oxidative stress, cellular and tissue damage, and secreted factors over the time period of 24 hours-1 week after irradiation with 0.25-0.5 Gy 5-ion simplified simulated galactic cosmic rays and 0.3-0.8 Gy high-LET 600MeV/n 56 Fe particles, and compared the outcomes to low-LET irradiation with 0.1-1 Gy doses of X-rays and gamma rays. Both high and low-LET radiation increased neurovascular permeability, caused oxidative stress, damaged endothelial cells and tight junctions, and altered expression of inflammatory cytokines. Ionizing radiation- induced neurovascular permeability and oxidative stress peaked at 3 days after irradiation and were further exacerbated by the presence of astrocytes. Furthermore, in response to particle irradiation, astrocytes stimulated interleukin-1 signaling by inhibiting the expression of interleukin-1 receptor antagonist. Thus, we also evaluated interleukin-1 receptor antagonist as a potential countermeasure against particle radiation. Ultimately, our results may help develop countermeasures to mitigate human CNS damage in deep space exploration.

Sonali D Verma↗
NASA NTRS2005

Use of Field Programmable Gate Array Technology in Future Space Avionics

Fulfilling NASA's new vision for space exploration requires the development of sustainable, flexible and fault tolerant spacecraft control systems. The traditional development paradigm consists of the purchase or fabrication of hardware boards with fixed processor and/or Digital Signal Processing (DSP) components interconnected via a standardized bus system. This is followed by the purchase and/or development of software. This paradigm has several disadvantages for the development of systems to support NASA's new vision. Building a system to be fault tolerant increases the complexity and decreases the performance of included software. Standard bus design and conventional implementation produces natural bottlenecks. Configuring hardware components in systems containing common processors and DSPs is difficult initially and expensive or impossible to change later. The existence of Hardware Description Languages (HDLs), the recent increase in performance, density and radiation tolerance of Field Programmable Gate Arrays (FPGAs), and Intellectual Property (IP) Cores provides the technology for reprogrammable Systems on a Chip (SOC). This technology supports a paradigm better suited for NASA's vision. Hardware and software production are melded for more effective development; they can both evolve together over time. Designers incorporating this technology into future avionics can benefit from its flexibility. Systems can be designed with improved fault isolation and tolerance using hardware instead of software. Also, these designs can be protected from obsolescence problems where maintenance is compromised via component and vendor availability.To investigate the flexibility of this technology, the core of the Central Processing Unit and Input/Output Processor of the Space Shuttle AP101S Computer were prototyped in Verilog HDL and synthesized into an Altera Stratix FPGA.

Ferguson, Roscoe C.↗
NASA NTRSDate not supplied

Pt/HTCC Alumina based Electronic Packaging System and Integration Processes for High Temperature Harsh Environment Applications

Electronic devices capable of operation at 500°C are required for long term Venus surface missions, as well as for in situ monitoring and control of next generation aeronautical engines. High temperature sensors and electronics can also find many applications in military, and energy and automobile industries. Various silicon carbide (SiC) sensors and electronic devices have been developed for operation at 500 °C, and a compatible packaging system is needed for long term test and deployment of these high temperature devices. High temperature co-fired ceramics (HTCC) alumina with platinum (Pt) conductor was proposed for high temperature electronic packaging. A prototype Pt/HTCC alumina packaging system including chip-level package and circuit board has been briefly reported previously for long-term electrical testing of SiC integrated circuits at 500 °C, and brief testing at much higher temperatures. HTCC alumina is an excellent dielectric material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. Pt is chemically noble and can be co-fired with HTCC alumina in air ambient producing a viable electronic packaging material system for high temperature applications. This paper presents a more detailed description of this packaging system including prototype low power packages and circuit boards based on HTCC alumina and Pt metallization for 500°C and other harsh environment applications. The key technical considerations for chip-level packaging and circuit board assembly, including materials and processes for 500 °C durable wire-bonding and SiC die attach, and integration of multi-chip circuit boards, are presented. Experimental test results of this packaging approach applied to SiC integrated circuits at 500 °C and 700°C are discussed as well.

High temperature↗
NASA NTRSDate not supplied

Pt/HTCC Alumina based Electronic Packaging System and Integration Processes for High Temperature Harsh Environment Applications

Electronic devices capable of operation at 500°C are required for long term Venus surface missions, as well as for in situ monitoring and control of next generation aeronautical engines. High temperature sensors and electronics can also find many applications in military, and energy and automobile industries. Various silicon carbide (SiC) sensors and electronic devices have been developed for operation at 500 °C, and a compatible packaging system is needed for long term test and deployment of these high temperature devices. High temperature co-fired ceramics (HTCC) alumina with platinum (Pt) conductor was proposed for high temperature electronic packaging. A prototype Pt/HTCC alumina packaging system including chip-level package and circuit board has been briefly reported previously for long-term electrical testing of SiC integrated circuits at 500 °C, and brief testing at much higher temperatures. HTCC alumina is an excellent dielectric material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. Pt is chemically noble and can be co-fired with HTCC alumina in air ambient producing a viable electronic packaging material system for high temperature applications. This paper presents a more detailed description of this packaging system including prototype low power packages and circuit boards based on HTCC alumina and Pt metallization for 500°C and other harsh environment applications. The key technical considerations for chip-level packaging and circuit board assembly, including materials and processes for 500 °C durable wire-bonding and SiC die attach, and integration of multi-chip circuit boards, are presented. Experimental test results of this packaging approach applied to SiC integrated circuits at 500 °C and 700°C are discussed as well.

electronic packaging↗
NASA NTRS2001

Advanced RF Front End Technology

The ability to achieve low-mass low-cost micro/nanospacecraft for Deep Space exploration requires extensive miniaturization of all subsystems. The front end of the Telecommunication subsystem is an area in which major mass (factor of 10) and volume (factor of 100) reduction can be achieved via the development of new silicon based micromachined technology and devices. Major components that make up the front end include single-pole and double-throw switches, diplexer, and solid state power amplifier. JPL's Center For Space Microsystems - System On A Chip (SOAC) Program has addressed the challenges of front end miniaturization (switches and diplexers). Our objectives were to develop the main components that comprise a communication front end and enable integration in a single module that we refer to as a 'cube'. In this paper we will provide the latest status of our Microelectromechanical System (MEMS) switches and surface micromachined filter development. Based on the significant progress achieved we can begin to provide guidelines of the proper system insertion for these emerging technologies. Additional information is contained in the original extended abstract.

Herman, M. I.↗
NASA NTRS2007

VLSI Design of a Turbo Decoder

A very-large-scale-integrated-circuit (VLSI) turbo decoder has been designed to serve as a compact, high-throughput, low-power, lightweight decoder core of a receiver in a data-communication system. In a typical contemplated application, such a decoder core would be part of a single integrated circuit that would include the rest of the receiver circuitry and possibly some or all of the transmitter circuitry, all designed and fabricated together according to an advanced communication-system-on-a-chip design concept. Turbo codes are forward-error-correction (FEC) codes. Relative to older FEC codes, turbo codes enable communication at lower signal-to-noise ratios and offer greater coding gain. In addition, turbo codes can be implemented by relatively simple hardware. Therefore, turbo codes have been adopted as standard for some advanced broadband communication systems.

Fang, Wai-Chi↗
NASA NTRS2000

Deep Space Systems Technology Program Future Deliveries

NASA is in a period of frequent launches of low cost deep space missions with challenging performance needs. The modest budgets of these missions make it impossible for each to develop its own technology, therefore, efficient and effective development and insertion of technology for these missions must be approached at a higher level than has been done in the past. The Deep Space Systems Technology Program (DSST), often referred to as X2000, has been formed to address this need. The program is divided into a series of "Deliveries" that develop and demonstrate a set of spacecraft system capabilities with broad applicability for use by multiple missions. The First Delivery Project, to be completed in 2001, will provide a one MRAD-tolerant flight computer, power switching electronics, efficient radioisotope power source, and a transponder with services at 8.4 GHz and 32 GHz bands. Plans call for a Second Delivery in late 2003 to enable complete deep space systems in the 10 to 50 kg class, and a Third Delivery built around Systems on a Chip (extreme levels of electronic and microsystems integration) around 2006. Formulation of Future Deliveries (past the First Delivery) is ongoing and includes plans for such developments as highly miniaturized digital/analog/power electronics, optical communications, multifunctional structures, miniature lightweight propulsion, advanced thermal control techniques, highly efficient radioisotope power sources, and a unified flight ground software architecture to support the needs of future highly intelligent space systems. All developments are targeted at broad applicability and reuse, and will be commercialized within the US.

Salvo, Christopher G.↗
NASA NTRS1994

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

Sewell, James S.↗
NASA NTRS1986

VLSI Reed Solomon decoder design

A Reed Solomon code is a highly efficient error correcting code that NASA will use in future space communication missions. A VLSI implementation of the decoder is presented that accepts data rates of 80 Mbits/second. A total of seven chips are needed and operate with the symbol clock being the system clock for the chip set. Approximately 1.65 billion Galois Field operations per second are achieved with this chip set.

Maki, Gary K.↗
NASA NTRS2000

Reliability Modeling of Microelectromechanical Systems Using Neural Networks

Microelectromechanical systems (MEMS) are a broad and rapidly expanding field that is currently receiving a great deal of attention because of the potential to significantly improve the ability to sense, analyze, and control a variety of processes, such as heating and ventilation systems, automobiles, medicine, aeronautical flight, military surveillance, weather forecasting, and space exploration. MEMS are very small and are a blend of electrical and mechanical components, with electrical and mechanical systems on one chip. This research establishes reliability estimation and prediction for MEMS devices at the conceptual design phase using neural networks. At the conceptual design phase, before devices are built and tested, traditional methods of quantifying reliability are inadequate because the device is not in existence and cannot be tested to establish the reliability distributions. A novel approach using neural networks is created to predict the overall reliability of a MEMS device based on its components and each component's attributes. The methodology begins with collecting attribute data (fabrication process, physical specifications, operating environment, property characteristics, packaging, etc.) and reliability data for many types of microengines. The data are partitioned into training data (the majority) and validation data (the remainder). A neural network is applied to the training data (both attribute and reliability); the attributes become the system inputs and reliability data (cycles to failure), the system output. After the neural network is trained with sufficient data. the validation data are used to verify the neural networks provided accurate reliability estimates. Now, the reliability of a new proposed MEMS device can be estimated by using the appropriate trained neural networks developed in this work.

Perera. J. Sebastian↗
NASA NTRSDate not supplied

A System to Provide Deterministic Flight Software Operation and Maximize Multicore Processing Performance: The Safe and Precise Landing – Integrated Capabilities Evolution (SPLICE) Datapath

A method and design are described for a system that processes multiple data streams, utilizing a multicore asymmetric processing architecture, that eliminates data interrupts to the application processors. The design supports a deterministic environment for flight software in NASA’s Safe and Precise Landing – Integrated Capabilities Evolution (SPLICE) project. The SPLICE project develops sensor, algorithm, and compute technologies for Precision Landing and Hazard Avoidance (PL&HA) capabilities. The compute technology for SPLICE is the Descent and Landing Computer (DLC). The DLC hosts several SPLICE algorithms with high computational resource requirements that must be executed in a real-time and deterministic manner. The software runs on a custom Single Board Computer (SBC), with a Xilinx Ultrascale+ Multiprocessor System-on-a-Chip (MPSoC). Input data for the flight software is from a variety of sensors, unique with respect to data rate and packet size. A data path between the SPLICE sensors and algorithms is designed to efficiently deliver this data to the flight software using the MPSoC asymmetric processing cores and Field Programmable Gate Array (FPGA) fabric. This is implemented in a manner that isolates the application processors running the flight software from interrupts associated with the input data. By leveraging real-time processors on the MPSoC, and a structure with the appropriate interfaces in the shared memory on the SBC, the flight software can use the full set of application processors. The available utilization for each processor in this set is also maximized for the SPLICE applications, providing a sufficiently deterministic execution environment without the cost and overhead of a real-time operating system.

heterogeneous processing system↗
NASA NTRS2023

A System to Provide Deterministic Flight Software Operation and Maximize Multicore Processing Performance: The Safe and Precise Landing – Integrated Capabilities Evolution (SPLICE) Datapath

A method and design are described for a system that processes multiple data streams, utilizing a multicore asymmetric processing architecture, that eliminates data interrupts to the application processors. The design supports a deterministic environment for flight software in NASA’s Safe and Precise Landing – Integrated Capabilities Evolution (SPLICE) project. The SPLICE project develops sensor, algorithm, and compute technologies for Precision Landing and Hazard Avoidance (PL&HA) capabilities. The compute technology for SPLICE is the Descent and Landing Computer (DLC). The DLC hosts several SPLICE algorithms with high computational resource requirements that must be executed in a real-time and deterministic manner. The software runs on a custom Single Board Computer (SBC), with a Xilinx Ultrascale+ Multiprocessor System-on-a-Chip (MPSoC). Input data for the flight software is from a variety of sensors, unique with respect to data rate and packet size. A data path between the SPLICE sensors and algorithms is designed to efficiently deliver this data to the flight software using the MPSoC asymmetric processing cores and Field Programmable Gate Array (FPGA) fabric. This is implemented in a manner that isolates the application processors running the flight software from interrupts associated with the input data. By leveraging real-time processors on the MPSoC, and a structure with the appropriate interfaces in the shared memory on the SBC, the flight software can use the full set of application processors. The available utilization for each processor in this set is also maximized for the SPLICE applications, providing a sufficiently deterministic execution environment without the cost and overhead of a real-time operating system.

David K. Rutishauser↗
NASA NTRS2015

Packaging Technologies for 500 C SiC Electronics and Sensors: Challenges in Material Science and Technology

This paper presents ceramic substrates and thick-film metallization based packaging technologies in development for 500C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550C. The 96 alumina packaging system composed of chip-level packages and PCBs has been successfully tested with high temperature SiC discrete transistor devices at 500C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC junction field-effect-transistor (JFET) with a packaging system composed of a 96 alumina chip-level package and an alumina printed circuit board was tested on low earth orbit for eighteen months via a NASA International Space Station experiment. In addition to packaging systems for electronics, a spark-plug type sensor package based on this high temperature interconnection system for high temperature SiC capacitive pressure sensors was also developed and tested. In order to further significantly improve the performance of packaging system for higher packaging density, higher operation frequency, power rating, and even higher temperatures, some fundamental material challenges must be addressed. This presentation will discuss previous development and some of the challenges in material science (technology) to improve high temperature dielectrics for packaging applications.

dielectric properties↗
NASA NTRS2000

Applications of SPICE for modeling miniaturized biomedical sensor systems

This paper proposes a model for a miniaturized signal conditioning system for biopotential and ion-selective electrode arrays. The system consists of three main components: sensors, interconnections, and signal conditioning chip. The model for this system is based on SPICE. Transmission-line based equivalent circuits are used to represent the sensors, lumped resistance-capacitance circuits describe the interconnections, and a model for the signal conditioning chip is extracted from its layout. A system for measurements of biopotentials and ionic activities can be miniaturized and optimized for cardiovascular applications based on the development of an integrated SPICE system model of its electrochemical, interconnection, and electronic components.

Microelectrodes↗
NASA NTRS2002

Flip chip packaging of a MEMS neuro-prosthetic system

A joint research team from California Institute of Technology and Jet Propulsion Laboratory is developing a fully miniaturized, smart implantable neuro-prosthetic system, by combining integrated electronics with Micro Electro Mechanical Structure (MEMS) based electrode arrays. The packaging group of this project team has been tasked with designing and fabricating a package to interface electrically between a MEMS electrode array, capable of extracting signals from brain, and an electronic chip, capable of providing on chip conditioning/processing of extracted data, while delivering the output data to a detector located outside the body.

flip↗
NASA NTRS1989

Data compression for Eos on-board SAR processor

A lightweight, low-power, real-time data compressor design for the Earth Observing System (Eos) onboard synthetic aperture radar (SAR) processor is presented. The implementation is based on VLSI design of a pipelined binary tree-searched vector quantizer (VQ), utilizing space-qualifiable 1.25-micron CMOS technology. The implementation exploits VLSI system design principles such as the modularity, regular data flow, simple interconnection, localized communication, simple global control, and parallel/pipelined processing. The overall system requires 30 chips with only one VLSI processing element design. The total weight is about 1.2 lbs, with an estimated power dissipation of approximately 4 watts operating at the maximum input data rate. The projected throughput rate exceeds 5 MHz.

Chang, C. Y.↗