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NASA NTRS · 20150023099

Packaging Technologies for 500 C SiC Electronics and Sensors: Challenges in Material Science and Technology

Abstract

This paper presents ceramic substrates and thick-film metallization based packaging technologies in development for 500C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550C. The 96 alumina packaging system composed of chip-level packages and PCBs has been successfully tested with high temperature SiC discrete transistor devices at 500C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC junction field-effect-transistor (JFET) with a packaging system composed of a 96 alumina chip-level package and an alumina printed circuit board was tested on low earth orbit for eighteen months via a NASA International Space Station experiment. In addition to packaging systems for electronics, a spark-plug type sensor package based on this high temperature interconnection system for high temperature SiC capacitive pressure sensors was also developed and tested. In order to further significantly improve the performance of packaging system for higher packaging density, higher operation frequency, power rating, and even higher temperatures, some fundamental material challenges must be addressed. This presentation will discuss previous development and some of the challenges in material science (technology) to improve high temperature dielectrics for packaging applications.

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Chen, Liang-Yu, Neudeck, Philip G., Behelm, Glenn M., Spry, David J., Meredith, Roger D., Hunter, Gary W.. 2015-10-04. Packaging Technologies for 500 C SiC Electronics and Sensors: Challenges in Material Science and Technology. https://ntrs.nasa.gov/citations/20150023099

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Importance of finite-size corrections for accurate ab initio modeling of carrier capture at semiconductor defects: A case study of substitutional C N in GaN

In ab initio studies of carrier-capture processes in defective semiconductor materials, the single-effective-mode formalism and the static-coupling approximation have become the predominant theoretical approaches for determining carrier-capture coefficients. The single-mode formalism relies on accurate nonequilibrium defect energies obtained from density-functional theory (DFT), where required inputs are a series of configurationally displaced, defect-containing supercells obtained using an interpolative ansatz, and where the DFT outputs are corresponding total energies that have traditionally been postprocessed using a long-established ground-state formulation of finite-size corrections and defect-formation energies. This formulation remains commonly used even though the defects that form a configuration-coordinate (CC) diagram typically exist as structures that are displaced from the ground state. To remedy this inconsistency, Kumagai has recently proposed novel methods for implementing finite-size corrections specifically intended for DFT calculations of the defect energies used to construct CC diagrams and implement the single-mode formalism [Y. Kumagai, Phys. Rev. B 107, L220101 (2023)]. Kumagai's approach builds on the latest finite-size-correction methods introduced to describe vertical charge-state transitions for charge-localizing point defects in semiconductors and insulators [T. Gake et al., Phys. Rev. B 101, 020102 (2020); S. Falletta et al., Phys. Rev. B 102, 041115 (2020)]. The newly identified finite-size artifact treated in these studies is the polarization charge induced on a configurationally frozen defect and its subsequent interaction with a vertical transition in charge state. In this work, we evaluate Kumagai's proposed methodology by applying it in a high-precision DFT study of carrier capture by substitutional C N in GaN, a well-characterized and technologically relevant defect and material. We have rigorously calculated C N defect energies across various supercell sizes for each defect configuration and charge state on the hole-capture CC diagram of C N (𝑞=−1), enabling a direct comparison of the slopes of the defect energies versus inverse cell size with those predicted by Kumagai. The most consequential prediction of Kumagai's method is that these slopes distinctly vary as the square of the linear-interpolation parameter used to construct the nonequilibrium defect configurations. Our results quantitatively support this prediction. Moreover, with these new finite-size corrections and multiple-cell-size DFT calculations in place, we find that the classical energy barrier for hole capture by C N (𝑞=−1) in GaN decreases to 0.092–0.127 eV. This finding confirms the recent ≈ 0.1 eV prediction of Reshchikov based on the weak temperature dependence for hole capture observed in photoluminescence experiments [M. A. Reshchikov, J. Appl. Phys. 129, 121101 (2021)]. These results stand in stark contrast to previously calculated barriers of 0.486 and 0.73 eV, which also used the single-mode formalism but were obtained by instead using ground-state-based finite-size corrections. Our reduced classical barrier for capture increases the temperature-dependent hole-capture coefficient of a C N (𝑞=−1) defect by more than two to four orders of magnitude for temperatures of 100–600 K, compared to the previous 0.486 eV results. While other defects may not be as dramatically affected as here, we suggest that incorporating proper finite-size corrections for the vertical-transition-like states embedded within CC diagrams is an essential, yet previously unrecognized, component of accurate modeling of carrier-capture when using the single-effective-mode formalism.

dielectric properties↗