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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 163 records · Page 9
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Heterogeneous integration of an electro-optical platform

A hybrid photonic integrated circuit and a method of its manufacture are provided. A SiP functional layer is fabricated on an SOI wafer. A lithium niobate thin film is bonded to the SiP functional layer. The silicon handle layer is removed from the SOI wafer to expose buried oxide, and at least one III-V die is bonded to the exposed buried oxide. In embodiments, at least one waveguiding component is fabricated in the SiP functional layer. In embodiments, the SiP functional layer comprises a top waveguiding layer.

Kodigala, Ashok↗
NASA NTRS2005

Hot-Electron Bolometer Mixers on Silicon-on-Insulator Substrates for Terahertz Frequencies

A terahertz Hot-Electron Bolometer (HEB) mixer design using device substrates based on Silicon-On-Insulator (SOI) technology is described. This substrate technology allows very thin chips (6 pm) with almost arbitrary shape to be manufactured, so that they can be tightly fitted into a waveguide structure and operated at very high frequencies with only low risk for power leakages and resonance modes. The NbTiN-based bolometers are contacted by gold beam-leads, while other beamleads are used to hold the chip in place in the waveguide test fixture. The initial tests yielded an equivalent receiver noise temperature of 3460 K double-sideband at a local oscillator frequency of 1.462 THz and an intermediate frequency of 1.4 GHz.

bolometer↗
DOE OSTI2025

A sub-5 ps jitter time-to-digital converter ASIC with back-gate delay tuning in 22 nm CMOS

We present the design of a Time-to-Digital Converter (TDC) ASIC together with performance characterization results at cryogenic temperature (6-8 K), and at room temperature using emulated Low-Gain Avalanche Detector (LGAD) signals. The TDC design uses a two-step architecture with a ring-oscillator based counter and a Vernier delay line fine TDC. The TDC is implemented in an FD-SOI process, and back-gate tuning is used not only to correct threshold variation due to cryogenic operation, but also as a novel way to tune TDC delay elements with very little overhead. Using this technique, we demonstrate a design with very low power (0.5 mW) and area (0.003 mm 2 ). We present test results using the Fermilab Constant Fraction Discriminator (FCFD) ASIC to produce discriminated signals from an internal charge injection mechanism that mimics the waveform and signal amplitude of minimum ionizing particles impinging on LGAD sensors. We characterize the time precision of the full system and verify that the TDC ASIC contributes a negligible amount to the total system time precision, fully consistent with the expected jitter contribution of less than 5 ps. In conclusion, the results presented here demonstrate the utility of our TDC for applications in physics and quantum communications.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2020

Spin Transport in Ferromagnet-InSb Nanowire Quantum Devices

Signatures of Majorana zero modes (MZMs), which are the building blocks for fault-tolerant topological quantum computing, have been observed in semiconductor nanowires (NW) with strong spin-orbital-interaction (SOI), such as InSb and InAs NWs with proximity-induced superconductivity. Realizing topological superconductivity and MZMs in this most widely-studied platform also requires eliminating spin degeneracy, which is realized by applying a magnetic field to induce a helical gap. Yet, the applied field can adversely impact the induced superconducting state in the NWs and also places geometric restrictions on the device, which can affect scaling of future MZM-based quantum registers. These challenges could be circumvented by integrating magnetic elements with the NWs. With this motivation, in this work we report the first experimental investigation of spin transport across InSb NWs, which are enabled by devices with ferromagnetic (FM) contacts. We determine signatures of spin polarization and spin-dependent transport in the quasi-one-dimensional ballistic regime. Moreover, we show that electrostatic gating tunes the observed magnetic signal and also reveals a transport regime where the device acts as a spin filter. These results open an avenue towards developing MZM devices in which spin degeneracy is lifted locally, without the need of an applied magnetic field. They further provide a path for realizing spin-based devices that leverage spin-orbital states in quantum wires.

1D ballistic spin transport↗
DOE OSTI2021

Opposite current-induced spin polarizations in bulk-metallic Bi 2 Se 3 and bulk-insulating Bi 2 Te 2 Se topological insulator thin flakes

One of the most fundamental and exotic properties of three-dimensional (3D) topological insulators (TIs) is spin-momentum locking (SML) of their topological surface states (TSSs), promising for potential applications in future spintronics. However, other possible conduction channels, such as a trivial two-dimensional electron gas (2DEG) with strong Rashba-type spin-orbit interaction (SOI) and bulk-conducting states that may possess a spin Hall effect (SHE), can coexist in 3D TIs, making determining the origin of the current-induced spin polarization (CISP) difficult. Here, we directly compared the CISP between bulk-insulating Bi 2 Te 2 Se (BTS221) and bulk-metallic Bi2Se3 thin flakes using spin potentiometry. In the bulk-insulating BTS221, the observed CISP has a sign consistent with the expected helicity of the SML of the TSS, but an opposite sign to its calculated bulk spin Hall conductivity. However, compared to BTS221, an opposite CISP is observed in the bulk-metallic Bi2Se3, consistent with both the expectations of its Rashba-Edelstein effect of the band-bending induced 2DEG and bulk intrinsic spin Hall Effect (SHE). If one assumes a representative occupation of the Rashba band of 3×10 13 cm –2 in Bi 2 Se 3 with a relevant relaxation time of 100 fs, the contribution to the CISP could be more dominated by the bulk intrinsic SHE. Our results provide an electrical way to distinguish the TSS from other possible conducting channels in spin transport measurements on 3D TIs, and open ways for the potential applications in charge-spin conversion devices.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2020

Micromachined Piezoresistive-sensed Diaphragms for Infrasonic Monitoring

Micromachined, piezoresistive-sensed diaphragms are designed and fabricated specifically for infrasound sensing applications. Relatively large diaphragms, up to 6 mm × 6 mm, are fabricated to meet the high sensitivity requirements of infrasonic monitoring. A double-stack SOI wafer process is used, resulting in a streamlined two-mask process without the need for doping or ion-implantation. Pressure-sensitivities of diaphragms are studied using a custom static calibration set-up. Here, the piezoresistance of longitudinal and transverse resistors are studied over a large pressure range of ±5,500 Pa so that the linear and nonlinear response regions of diaphragms are observed. Measurements are compared against a nonlinear finite element simulation—shown to accurately predict the sensor’s behavior over a large response range.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

A 0.2–2 GHz Time-Interleaved Multistage Switched-Capacitor Delay Element Achieving 2.55–448.6 ns Programmable Delay Range and 330 ns/mm 2 Area Efficiency

Simulation of radar returns, full-duplex systems, and signal repeaters require hundreds of ns of programmable broadband radio frequency (RF) delay in the signal path to simulate large distances in the case of radar returns, for signal cancellation in full-duplex, and for isolation from reflections in signal repeaters. However, programmable broadband RF delay has been limited to ones of ns due to challenges in miniaturization with low loss and low power consumption. In this work, we present a 0.2–2 GHz digitally programmable RF delay element based on a time-interleaved multistage switched-capacitor (TIMS-SC) approach. The proposed approach enables hundreds of ns of broadband RF delay by employing sample time expansion in multiple stages of switched-capacitor storage elements. Further, the delay element was implemented in a 45 nm SOI CMOS process and achieves a 2.55–448.6 ns programmable delay range with < 0.12% delay variation across 1.8 GHz of bandwidth at maximum delay, 2.42 ns programmable delay steps, and 330 ns/mm 2 area efficiency. Through the proposed approach, the device shows minimal delay change across a -40 °C to 85 °C temperature range and < 0.25 dB gain variation across delay settings. The device achieves 26 dB gain, 7.4 dB noise figure, and consumes 74 mW from a 1 V supply with an active area of 1.36 mm 2 .

42 ENGINEERING↗
DOE OSTI2022

Mid-Infrared Nonlinear Frequency Conversion Using Monolithic Barium Titanate on Silicon-on-Insulator

In this work, efficient nonlinear frequency conversion in the mid-infrared (mid-IR) region was demonstrated by a barium titanate (BTO) on a silicon-on-insulator (SOI) substrate. The BTO thin film was epitaxially grown by pulsed-laser deposition (PLD). The tensorial second order optical nonlinearity and the ferroelectric domain property of the BTO were characterized by the polarimetric mid-IR second harmonic generation (SHG) measurements. Azimuthal-dependent polarized SHG was modeled at different combinations of the nonlinear coefficient $d_{ij}$ and the domain fraction factor $ΔD^Y/ΔD^X$. Strong SHG intensity was experimentally observed over a broad spectrum at λ = 3.1 μm - 3.7 μm. A characteristic linear dependence between the SHG signal and the square of the pumping laser intensity was observed. The monolithic integration between the epitaxial BTO and the Si provides a compact platform for efficient on-chip light generation and quantum photonic technologies.

25 ENERGY STORAGE↗
DOE OSTI2023

Buried-Electrode Hybrid Bonded Thin-Film Lithium Niobate Electro-Optic Mach-Zehnder Modulators

Hybrid bonded silicon nitride thin-film lithium niobate (TFLN) Mach-Zehnder modulators (MZMs) at 1310 nm were designed with metal coplanar waveguide electrodes buried in the silicon-on-insulator (SOI) chip. Here, the MZM devices showed greatly improved performance compared to earlier devices of a similar design, and similar performance to comparable MZM devices with gold electrodes made on top of the TFLN layer. Both devices achieve a 3-dB electro-optic bandwidth greater than 110 GHz and voltage-driven optical extinction ratios greater than 28 dB. Half-wave voltage-length products (VπL) of 2.8 and 2.5 V∙ cm were measured for the 0.5 and 0.4 cm long buried metal and top gold electrode MZMs, respectively.

42 ENGINEERING↗
DOE OSTI2024

A 32-Channel Cryo-CMOS ASIC for SNSPD Biasing and Readout with Picosecond

Superconducting nanowire single-photon detectors (SNSPD) are a promising technology for particle detection. Although SNSPDs have demonstrated picosecond timing accuracy, scaling up large arrays has proved challenging. In this work, we introduce a 32-channel cryo-CMOS application-specific integrated circuit (ASIC) that can be tightly integrated with SNSPD arrays. The ASIC is designed to operate at a temperature of 4K and can perform up to 32 simultaneous timing measurements with a root-mean-square (RMS) accuracy of 8.0ps. The ASIC includes on-chip circuitry for externally biasing superconducting devices, low-noise amplifiers for reading superconducting devices, high-resolution time-to-digital converters (TDC) for time-tagging events, and serializers for transmitting data to room-temperature electronics. The ASIC is manufactured in a 22nm FDSOI process and occupies an area of 4.0mm x 1.0mm. The performance of the ASIC was verified using custom cryogenic device models internally developed for the 22nm SOI process. Measurement results will be presented at the conference.

Fredenburg, Jeff↗
DOE OSTI2026

Cryogenic-Refined MOSFET Modeling for Oscillator, Frequency Divider, and Amplifier Designs Below 4 K

Capturing device characteristic changes at cryogenic temperatures is crucial for cryo-CMOS circuit designs. In this work, we present an isothermal cryogenic-refined modeling approach for CMOS transistors that is simple, low overhead, and easy to implement while offering the required accuracy for predicting circuit performance at the designated temperatures. Guided by die-level measurement data and circuit design principles, the model introduces corrections to only five critical parameters: threshold voltage, carrier mobility, elevated low-frequency flicker noise, dominant high-frequency shot noise, and subthreshold swing (SS). These refinements are implemented around the foundry-provided SPICE model, which is typically validated only down to about 200 K. With these adjustments, the proposed cryogenic-refined model achieves less than 5% error in both large-signal metrics (I–V characteristics) and small-signal parameters (e.g., transconductance) when compared with device measurements at deep-cryogenic temperatures. The methodology is validated in two advanced technologies: TSMC 40-nm CMOS and GlobalFoundries (GF) 45-nm RF-SOI. We further demonstrate its applicability in three representative RF circuits: a 30-GHz LC oscillator, a high-speed current-mode-logic (CML) frequency divider (FD), and a subthreshold Gb/s amplifier, all showing close agreement between simulated predictions and measurements performed at 4 and 2.5 K. Finally, we believe that the proposed approach is implementation-friendly and can significantly accelerate the development of cryo-CMOS integrated circuits.

circuit modeling↗
DOE OSTI2026

Catapult-ASIC-dev

This branch extends the wa-hls4ml (FERMILAB-CODE-2026-09-CSAID) work to ASIC technology nodes (Nangate 45 nm and GlobalFoundries 22FDX FD-SOI) using Siemens Catapult HLS. Code is available at: https://github.com/fastmachinelearning/wa-hls4ml-paper/tree/Catapult-ASIC-dev

Di Guglielmo, Giuseppe [Fermi National Accelerator↗
DOE OSTI2023

Hierarchical multi-time-scale predictive thermal management and fuel optimization for heavy-duty compression ignition engines

For heavy-duty diesel engines, NO X emissions reduction is strongly constrained by fuel efficiency. This paper presents a hierarchical model predictive controller (H-MPC) for coordinated control of tailpipe NO X emissions and fuel consumption. The H-MPC uses the separation of slow and fast dynamics that exist in the engine and its aftertreatment system. The controller is synthesized with an architecture in which a high-level MPC uses a longer prediction horizon compared to the low-level predictive controller which tracks the high-level controller command and manages the thermal dynamics of the aftertreatment system. Engine load preview enables the high-level controller to estimate the desired catalyst temperature ahead of time and addresses the selective catalytic reduction (SCR) slow thermal dynamics. Calculated by the high-level controller, the intake manifold pressure, and the start of injection (SOI) crank angle is used as reference trajectories in the low-level controller that regulates fast dynamical behaviors such as engine out NO X emissions. Hardware-in-the-loop (HIL) validation of this integrated H-MPC on a rapid prototype controller shows that when the SCR catalyst temperature is above light-off temperature (warmed-up condition), the engine operation is shifted to operate with the best fuel economy since the warmed-up SCR can efficiently reduce the engine-out NO X emissions. Results indicate that up to 0.8% benefit in cycle averaged BSFC along with a 13% reduction in tailpipe NO X compared to a stock engine calibration can be achieved with the coordinated engine and aftertreatment system through H-MPC.

Engineering↗
DOE OSTI2024

Development of prechamber enabled mixing-controlled combustion strategy for ultra-low methane emissions from lean burn natural gas engines

This numerical study explores the optimization of Prechamber Enabled Mixing-Controlled Combustion (PC-MCC) using natural gas in heavy-duty engines, aiming to enhance combustion efficiency to minimize methane slip and NOx emissions. The approach involves a prechamber ignition system, distinct from conventional spark ignition (SI) systems, to initiate combustion of direct injected natural gas. By leveraging the robust ignition characteristics of the prechamber, the PC-MCC method demonstrates significant potential in achieving efficient combustion akin to diesel engines but with lower greenhouse gas emissions. The research evaluates the effects of various geometric and operational parameters on the combustion process and emissions, including prechamber volume, nozzle diameter, direct injector (DI) geometry, and engine operating strategies. Computational Fluid Dynamics (CFD) simulations are utilized, focusing on a heavy-duty, single-cylinder engine modeled after the Caterpillar C9.3B engine. Key findings indicate that a prechamber volume of 3 cc, coupled with a nozzle diameter of 2.75 mm for two prechamber holes, strikes an optimal balance between combustion efficiency and emissions reduction. This configuration ensures robust combustion across a range of operating conditions while maintaining methane slip within targeted limits. Further investigation into DI geometry shows the significance of the injector umbrella angle and nozzle diameter in shaping the fuel-air mixing and combustion dynamics. An umbrella angle of 130° and a nozzle diameter of 300 microns are identified as optimal, promoting rapid and efficient combustion with minimized methane and NOx emissions. The study also investigates the impact of injection timing and pressure, highlighting their roles in controlling combustion timing and influencing emissions levels. Advanced injection timing is found to be crucial in achieving the desired low methane slip, whereas retarded injection timing assists to reduce NOx emissions while having a slight increase in methane emissions. Operating strategies incorporating various levels of Exhaust Gas Recirculation (EGR) are assessed for their effectiveness in further reducing emissions. The research demonstrates that a judicious combination of internal hot EGR and careful calibration of DI pressure and SOI timing can achieve significant reductions in NOx emissions while keeping methane slip under control. Specifically, an internal EGR level of 15%–25%, combined with DI pressures of 200–300 bar and injection timings at or after top dead center, is recommended. These findings contribute valuable insights into the development of advanced combustion techniques for natural gas engines, offering a viable pathway to reduce methane slip without compromising engine efficiency or performance. The PC-MCC system presents a promising solution for the future of heavy-duty natural gas engine technology to reduce methane emissions.

Nsaif, Osama↗
DOE OSTI2023

Fabrication-robust silicon photonic devices in standard sub-micron silicon-on-insulator processes

Perturbations to the effective refractive index from nanometer-scale fabrication variations in waveguide geometry plague high index-contrast photonic platforms; this includes the ubiquitous sub-micron silicon-on-insulator (SOI) process. Such variations are particularly troublesome for phase-sensitive devices, such as interferometers and resonators, which exhibit drastic changes in performance as a result of these fabrication-induced phase errors. In this Letter, we propose and experimentally demonstrate a design methodology for dramatically reducing device sensitivity to silicon width variations. We apply this methodology to a highly phase-sensitive device, the ring-assisted Mach–Zehnder interferometer (RAMZI), and show comparable performance and footprint to state-of-the-art devices, while substantially reducing stochastic phase errors from etch variations. This decrease in sensitivity is directly realized as energy savings by significantly reducing the required corrective thermal tuning power, providing a promising path toward ultra-energy-efficient large-scale silicon photonic circuits.

Rizzo, Anthony (ORCID:000000034752797X)↗
DOE OSTI2024

A 32-Channel Cryo-CMOS ASIC for SNSPD Biasing and Readout with Picosecond Timing

Superconducting nanowire single-photon detectors (SNSPD) are a promising technology for particle detection. Although SNSPDs have demonstrated picosecond timing accuracy, scaling up large arrays has proved challenging. In this work, we introduce a 32-channel cryo-CMOS application-specifc integrated circuit (ASIC) that can be tightly integrated with SNSPD arrays. The ASIC is designed to operate at a temperature of 4K and can perform up to 32 simultaneous timing measurements with a root-mean-square (RMS) accuracy of 8.0ps. The ASIC includes on-chip circuitry for externally biasing superconducting devices, low-noise amplifers for reading superconducting devices, high-resolution time-to-digital converters (TDC) for time-tagging events, and serializers for transmitting data to room-temperature electronics. The ASIC is manufactured in a 22nm FDSOI process and occupies an area of 4.0mm x 1.0mm. The performance of the ASIC was verifed using custom cryogenic device models internally developed for the 22nm SOI process. Measurement results will be presented at the conference.

Fredenburg, Jeff↗