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This presentation is for the NSSC Fall workshop. I will be presenting both my work during my Sandia internship as well as my research at UIUC.
A polarimeter was designed for high spatial and spectral resolution. It consists of a quarter-wave plate alternately operating in two positions for Stoke-V measurements and an additional quarter-wave plate for Stokes-U and -Q measurements. The spatial range covers 75 arcsec, the spectral window of about 1.8 a allows the simultaneous observations of neighboring lines. The block diagram of the data processing and acquisition system consists of five memories each one having a capacity of 10 to the 4th power 16-bit words. The total time to acquire profiles of Stokes parameters can be chosen by selecting the number of successive measurements added in the memories, each individual measurement corresponding to an integration time of 0.5 sec. Typical values range between 2 and 60 sec depending on the brightness of the structure, the amount of polarization and a compromise between desired signal-to-noise ratio and spatial resolution.
The accuracy is studied of temperature estimates derived from the divergence equation when wind observations of various spatial and temporal resolutions and accuracies are available. The basic data set used is the high resolution model data set used by Kuo and Anthes (1984a) in observing systems simulation experiments (OSSE) designed to estimate the errors in heat and moisture budgets (Kuo and Anthes, 1984b) calculated from the AVE-SESAME-1979 spatial observational network. This model data set is modified in ways to simulate wind observations that appear feasible from an operational regional network of wind profilers.
Friction Stir Welds (FSW) of A1 2195-T8 and A1 2219-T8, provided by Lockheed Martin Michoud Operations, were inspected for lack-of-penetration (LOP) defects using a custom designed MWM-Array, a multi-element eddy-current sensor. MWM electrical conductivity mapping demonstrated high sensitivity to LOP as small as 0.75 mm (0.03 in.), as confirmed by metallographic data that characterized the extent of LOP defects. High sensitivity and high spatial resolution was achieved via a 37-element custom designed MWM-Array allowing LOP detection using the normalized longitudinal component of the MWM measured conductivity. This permitted both LOP detection and correlation of MWM conductivity features with the LOP defect size, as changes in conductivity were apparently associated with metallurgical features within the near-surface layer of the LOP defect zone. MWM conductivity mapping reveals information similar to macroetching as the MWM-Array is sensitive to small changes in conductivity due to changes in microstructure associated with material thermal processing, in this case welding. The electrical conductivity measured on the root side of FSWs varies across the weld due to microstructural differences introduced by the FSW process, as well as those caused by planar flaws. Weld metal, i.e., dynamically recrystallized zone (DXZ), thermomechanically affected zone (TMZ), heat-affected zone (HAZ), and parent metal (PM) are all evident in the conductivity maps. While prior efforts had met with limited success for NDE of dissimilar alloy, A12219 to A12195 FSW, the new custom designed multi-element MWM-Array achieved detection of all LOP defects even in dissimilar metal welds.
This article focuses on the properties of a fine grained reconfigurable transistor array currently under test at the Jet Propulsion Laboratory (JPL).
Evolvable Hardware (EHW) refers to HW design and self-reconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, describing also a set of selected applications.
Gamma irradiation and annealing of a large number of Actel FPGAs with in-situ current measurements were performed. Lot-to-lot, part-to-part, and burn in variations were measured. Findings include a catastrophic failure mechanism and minimal dose rate effects.
This paper describes a rapid, top down requirements-driven design of an FPGA used in an Earth qualification test program for a new Mars subsonic parachute. The FPGA is used to process and control storage of telemetry data from multiple sensors throughout; launch, ascent, deployment and descent phases of the subsonic parachute test.
We present initial results for the thin epitaxial Xilinx Virtex-4 Fie ld Programmable Gate Array (FPGA), and compare to previous results ob tained for the Virtex-II and Virtex-II Pro. The data presented was a cquired through a consortium based effort with the common goal of pr oviding the space community with data and mitigation methods for the use of Xilinx FPGAs in space.
Motivation for this work is: (1) Accurately characterize digital signal processor (DSP) core single-event effect (SEE) behavior (2) Test DSP cores across a large frequency range and across various input conditions (3) Isolate SEE analysis to DSP cores alone (4) Interpret SEE analysis in terms of single-event upsets (SEUs) and single-event transients (SETs) (5) Provide flight missions with accurate estimate of DSP core error rates and error signatures.
We present a novel method of FPGA TID testing that measures propagation delay between flip-flops operating at maximum speed. Measurement is performed on-chip at-speed and provides a key design metric when building system-critical synchronous designs.
An apparatus is provided that includes a plurality of modules, a plurality of memory banks, and a multiplexor. Each module includes at least one agent that interfaces between a module and a memory bank. Each memory bank includes an arbiter that interfaces between the at least one agent of each module and the memory bank. The multiplexor is configured to assign data paths between the at least one agent of each module and a corresponding arbiter of each memory bank based on the assigned data path. The at least one agent of each module is configured to read data from the corresponding arbiter of the memory bank or write modified data to the corresponding arbiter of the memory bank.
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An overview of the 2020 single event effects FPGA effort performed by the NASA Electronic Parts and Packaging Group is presented. Information includes Heavy-ion data for the following FPGA devices: Xilinx Kintex-UltraScale and Microsemi PolarFire. Future work is presented.
Irradiations and subsequent failure analyses were performed to investigate single event dielectric rupture (SEDR) in Actel FPGAs as a function of ion LET, angle, bias, temperature, feature size, and device type. The small cross sections imply acceptably low risk for most spacecraft uses.