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NASA NTRS2003

Artifacts for Calibration of Submicron Width Measurements

Artifacts that are fabricated with the help of molecular-beam epitaxy (MBE) are undergoing development for use as dimensional calibration standards with submicron widths. Such standards are needed for calibrating instruments (principally, scanning electron microscopes and scanning probe microscopes) for measuring the widths of features in advanced integrated circuits. Dimensional calibration standards fabricated by an older process that involves lithography and etching of trenches in (110) surfaces of single-crystal silicon are generally reproducible to within dimensional tolerances of about 15 nm. It is anticipated that when the artifacts of the present type are fully developed, their critical dimensions will be reproducible to within 1 nm. These artifacts are expected to find increasing use in the semiconductor-device and integrated- circuit industries as the width tolerances on semiconductor devices shrink to a few nanometers during the next few years. Unlike in the older process, one does not rely on lithography and etching to define the critical dimensions. Instead, one relies on the inherent smoothness and flatness of MBE layers deposited under controlled conditions and defines the critical dimensions as the thicknesses of such layers. An artifact of the present type is fabricated in two stages (see figure): In the first stage, a multilayer epitaxial wafer is grown on a very flat substrate. In the second stage, the wafer is cleaved to expose the layers, then the exposed layers are differentially etched (taking advantage of large differences between the etch rates of the different epitaxial layer materials). The resulting structure includes narrow and well-defined trenches and a shelf with thicknesses determined by the thicknesses of the epitaxial layers from which they were etched. Eventually, it should be possible to add a third fabrication stage in which durable, electronically inert artifacts could be replicated in diamondlike carbon from a master made by MBE and etching as described above.

Grunthaner, Frank↗

NASA NTRS2008

Stable Electrical Operation of 6H-SiC JFETs and ICs for Thousands of Hours at 500 C

The fabrication and testing of the first semiconductor transistors and small-scale integrated circuits (ICs) to achieve up to 3000 h of stable electrical operation at 500 C in air ambient is reported. These devices are based on an epitaxial 6H-SiC junction field-effect transistor process that successfully integrated high temperature ohmic contacts, dielectric passivation, and ceramic packaging. Important device and circuit parameters exhibited less than 10% of change over the course of the 500 C operational testing. These results establish a new technology foundation for realizing durable 500 C ICs for combustion-engine sensing and control, deep-well drilling, and other harsh-environment applications.

Neudeck, Philip G.↗

NASA NTRS1981

Whatever happened to silicon carbide

The progress made in silicon carbide semiconductor devices in the 1955 to 1975 time frame is examined and reasons are given for the present lack of interest in the material. Its physical and chemical properties and methods of preparation are discussed. Fabrication techniques and the characteristics of silicon carbide devices are reviewed. It is concluded that a combination of economic factors and the lack of progress in fabrication techniques leaves no viable market for SiC devices in the near future.

Campbell, R. B.↗

NASA NTRS1994

Cubic GaS: A Surface Passivator For GaAs

Thin films of cubic form of gallium sulfide (GaS) formed on surfaces of gallium arsenide (GaAs) substrates via metal/organic chemical vapor deposition (MOCVD). Deposited cubic GaS, crystalline lattice matched to substrate GaAs, neutralizes electrically active defects on surfaces of both n-doped and p-doped GaAs. Enabling important GaAs-based semiconducting materials to serve as substrates for metal/insulator/semiconductor (MIS) capacitors. Cubic GaS enables fabrication of ZnSe-based blue lasers and light-emitting diodes. Because GaS is optically transparent, deposited to form window layers for such optoelectronic devices as light-emitting diodes, solar optical cells, and semiconductor lasers. Its transparency makes it useful as interconnection material in optoelectronic integrated circuits. Also useful in peeled-film technology because selectively etched from GaAs.

Hepp, Aloysius F.↗

NASA NTRS2006

Highly Efficient Multilayer Thermoelectric Devices

Multilayer thermoelectric devices now at the prototype stage of development exhibit a combination of desirable characteristics, including high figures of merit and high performance/cost ratios. These devices are capable of producing temperature differences of the order of 50 K in operation at or near room temperature. A solvent-free batch process for mass production of these state-of-the-art thermoelectric devices has also been developed. Like prior thermoelectric devices, the present ones have commercial potential mainly by virtue of their utility as means of controlled cooling (and/or, in some cases, heating) of sensors, integrated circuits, and temperature-critical components of scientific instruments. The advantages of thermoelectric devices for such uses include no need for circulating working fluids through or within the devices, generation of little if any noise, and high reliability. The disadvantages of prior thermoelectric devices include high power consumption and relatively low coefficients of performance. The present development program was undertaken in the hope of reducing the magnitudes of the aforementioned disadvantages and, especially, obtaining higher figures of merit for operation at and near room temperature. Accomplishments of the program thus far include development of an algorithm to estimate the heat extracted by, and the maximum temperature drop produced by, a thermoelectric device; solution of the problem of exchange of heat between a thermoelectric cooler and a water-cooled copper block; retrofitting of a vacuum chamber for depositing materials by sputtering; design of masks; and fabrication of multilayer thermoelectric devices of two different designs, denoted I and II. For both the I and II designs, the thicknesses of layers are of the order of nanometers. In devices of design I, nonconsecutive semiconductor layers are electrically connected in series. Devices of design II contain superlattices comprising alternating electron-acceptor (p)-doped and electron-donor (n)-doped, nanometer- thick semiconductor layers.

Boufelfel, Ali↗

NASA NTRS1996

Scaling Properties of Algorithms in Nanotechnology

At the present time, several technologies are pressing the limits of microminiature manufacturing. In semiconductor technology, for example, the Intel Pentium Pro (which is used in the Department of Energy's ASCI 'red' parallel supercomputer system) and the DEC Alpha 21164 (which is used in the CRAY T3E) both are fabricated using 0.35 micron process technology. Recently Texas Instruments (TI) announced the availability of 0.25 micron technology chips by the end of 1996 and plans to have 0.18 micron devices in production within two years. However, some significant challenges lie down the road. These include the skyrocketing cost of manufacturing plants, the 0.1 micron foreseeable limit of the photolithography process, quantum effects, data communication bandwidth limitations, heat dissipation, and others. Some related microminiature technologies include micro-electromechanical systems (MEMS), opto-electronic devices, quantum computing, biological computing, and others. All of these technologies require the fabrication of devices whose sizes are approaching the nanometer level. As such they are often collectively referred to with the name 'nanotechnology'. Clearly nanotechnology in this general sense is destined to be a very important technology of the 21st century. The ultimate dream in this arena is 'molecular nanotechnology', in other words the fabrication of devices and materials with most or all atoms and molecules in a pre-programmed position, possibly placed there by 'nano-robots'. This futuristic capability will probably not be achieved for at least two decades. However, it appears that somewhat less ambitious variations of molecular nanotechnology, such as devices and materials based on 'buckyballs' and 'nanotubes' may be realized significantly sooner, possibly within ten years or so. Even at the present time, semiconductor devices are approaching the regime where quantum chemical effects must be considered in design.

Saini, Subhash↗

NASA NTRS1990

High-temperature electronics

To meet the needs of the aerospace propulsion and space power communities, the high temperature electronics program at the Lewis Research Center is developing silicon carbide (SiC) as a high temperature semiconductor material. This program supports a major element of the Center's mission - to perform basic and developmental research aimed at improving aerospace propulsion systems. Research is focused on developing the crystal growth, characterization, and device fabrication technologies necessary to produce a family of SiC devices.

Matus, Lawrence G.↗

NASA NTRS1993

Design of power electronics for TVC EMA systems

The Composite Development Division of the Propulsion Laboratory at Marshall Space Flight Center (MSFC) is currently developing a class of electromechanical actuators (EMA's) for use in space transportation applications such as thrust vector control (TVC) and propellant control valves (PCV). These high power servomechanisms will require rugged, reliable, and compact power electronic modules capable of modulating several hundred amperes of current at up to 270 volts. MSFC has selected the brushless dc motor for implementation in EMA's. This report presents the results of an investigation into the applicability of two new technologies, MOS-controlled thyristors (MCT's) and pulse density modulation (PDM), to the control of brushless dc motors in EMA systems. MCT's are new power semiconductor devices, which combine the high voltage and current capabilities of conventional thyristors and the low gate drive requirements of metal oxide semiconductor field effect transistors (MOSFET's). The commanded signals in a PDM system are synthesized using a series of sinusoidal pulses instead of a series of square pulses as in a pulse width modulation (PWM) system. A resonant dc link inverter is employed to generate the sinusoidal pulses in the PDM system. This inverter permits zero-voltage switching of all semiconductors which reduces switching losses and switching stresses. The objectives of this project are to develop and validate an analytical model of the MCT device when used in high power motor control applications and to design, fabricate, and test a prototype electronic circuit employing both MCT and PDM technology for controlling a brushless dc motor.

Nelms, R. Mark↗

NASA NTRS1998

Semiconductors: In Situ Processing of Photovoltaic Devices

The possible processing of semiconductor photovoltaic devices is discussed. The requirements for lunar PV cells is reviewed, and the key challenges involved in their manufacturing are investigated. A schematic diagram of a passivated emitter and rear cell (PERC) is presented. The possible fabrication of large photovoltaic arrays in space from lunar materials is also discussed.

Curreri, Peter A.↗

NASA NTRS2000

Packaging Technology Developed for High-Temperature SiC Sensors and Electronics

A ceramic- and thick-film-materials-based prototype electronic package designed for silicon carbide (SiC) high-temperature sensors and electronics has been successfully tested at 500 C in an oxygen-containing air environment for 500 hours. This package was designed, fabricated, assembled, and electronically evaluated at the NASA Glenn Research Center at Lewis Field with an in-house-fabricated SiC semiconductor test chip. High-temperature electronics and sensors are necessary for harsh-environment space and aeronautical applications, such as space missions to the inner solar system or the emission control electronics and sensors in aeronautical engines. Single-crystal SiC has such excellent physical and chemical material properties that SiC-based semiconductor electronics can operate at temperatures over 600 C, which is significantly higher than the limit for Si-based semiconductor devices. SiC semiconductor chips were recently demonstrated to be operable at temperatures as high as 600 C, but only in the probe station environment because suitable packaging technology for sensors and electronics at temperatures of 500 C and beyond did not exist. Thus, packaging technology for SiC-based sensors and electronics is immediately needed for both application and commercialization of high-temperature SiC sensors and electronics. In response to this need, researchers at Glenn designed, fabricated, and assembled a prototype electronic package for high-temperature electronics, sensors, and microelectromechanical systems (MEMS) using aluminum nitride (AlN) substrate and gold (Au) thick-film materials. This prototype package successfully survived a soak test at 500 C in air for 500 hours. Packaging components tested included thick-film high-temperature metallization, internal wire bonds, external lead bonds, and a SiC diode chip die-attachment. Each test loop, which was composed of thick-film printed wire, wire bond, and lead bond was subjected to a 50-mA direct current for 250 hours at 500 C.

Chen, Liang-Yu↗

NASA NTRS1991

Growing Cobalt Silicide Columns In Silicon

Codeposition by molecular-beam epitaxy yields variety of structures. Proposed fabrication process produces three-dimensional nanometer-sized structures on silicon wafers. Enables control of dimensions of metal and semiconductor epitaxial layers in three dimensions instead of usual single dimension (perpendicular to the plane of the substrate). Process used to make arrays of highly efficient infrared sensors, high-speed transistors, and quantum wires. For fabrication of electronic devices, both shapes and locations of columns controlled. One possible technique for doing this electron-beam lithography, see "Making Submicron CoSi2 Structures on Silicon Substrates" (NPO-17736).

Fathauer, Obert W.↗

NASA NTRS1994

Improved Ferroelectric Memories With Nondestructive Readout

Ferroelectric memories with enhanced photoresponse leading to improved nondestructive optoelectronic readout and lower power demand proposed. Memories improved versions of devices described in "Rapid, Nondestructive Readout From Ferroelectric Memory" (NPO-18551). In proposed application, array of nonvolatile ferroelectric memory cells fabricated by standard very-large-scale integrated-circuit techniques and flip-bonded onto similarly fabricated array of semiconductor lasers, {see "Optically Addressable, Ferroelectric Memory With NDRO" (NPO-18573)}.

Thakoor, Sarita↗

NASA NTRS1988

Incoherent GaAlAs/GaAs semiconductor laser arrays

The fabrication of an incoherent laser array is reported. The main features of the arrays are low threshold index-guided laser elements, single-lobe far-field pattern, low astigmatism, low current operation, dense packing, and total electrical and optical isolation. With further development, this device should have applications in multihead optical-disk reading and writing, multifiber optical communications, and line-of-sight communications.

Hwang, C. J.↗

NASA NTRS2001

MEMS Device Being Developed for Active Cooling and Temperature Control

High-capacity cooling options remain limited for many small-scale applications such as microelectronic components, miniature sensors, and microsystems. A microelectromechanical system (MEMS) is currently under development at the NASA Glenn Research Center to meet this need. It uses a thermodynamic cycle to provide cooling or heating directly to a thermally loaded surface. The device can be used strictly in the cooling mode, or it can be switched between cooling and heating modes in milliseconds for precise temperature control. Fabrication and assembly are accomplished by wet etching and wafer bonding techniques routinely used in the semiconductor processing industry. Benefits of the MEMS cooler include scalability to fractions of a millimeter, modularity for increased capacity and staging to low temperatures, simple interfaces and limited failure modes, and minimal induced vibration.

Moran, Matthew E.↗

NASA NTRS2007

Focal-Plane Arrays of Quantum-Dot Infrared Photodetectors

Focal-plane arrays of semiconductor quantum-dot infrared photodetectors (QDIPs) are being developed as superior alternatives to prior infrared imagers, including imagers based on HgCdTe devices and, especially, those based on quantum-well infrared photodetectors (QWIPs). HgCdTe devices and arrays thereof are difficult to fabricate and operate, and they exhibit large nonunformities and high 1/f (where f signifies frequency) noise. QWIPs are easier to fabricate and operate, can be made nearly uniform, and exhibit lower 1/f noise, but they exhibit larger dark currents, and their quantization only along the growth direction prevents them from absorbing photons at normal incidence, thereby limiting their quantum efficiencies. Like QWIPs, QDIPs offer the advantages of greater ease of operation, greater uniformity, and lower 1/f noise, but without the disadvantages: QDIPs exhibit lower dark currents, and quantum efficiencies of QDIPs are greater because the three-dimensional quantization of QDIPs is favorable to the absorption of photons at normal or oblique incidence. Moreover, QDIPs can be operated at higher temperatures (around 200 K) than are required for operation of QWIPs. The main problem in the development of QDIP imagers is to fabricate quantum dots with the requisite uniformity of size and spacing. A promising approach to be tested soon involves the use of electron-beam lithography to define the locations and sizes of quantum dots. A photoresist-covered GaAs substrate would be exposed to the beam generated by an advanced, high-precision electron beam apparatus. The exposure pattern would consist of spots typically having a diameter of 4 nm and typically spaced 20 nm apart. The exposed photoresist would be developed by either a high-contrast or a low-contrast method. In the high-contrast method, the spots would be etched in such a way as to form steep-wall holes all the way down to the substrate. The holes would be wider than the electron beam spots perhaps as wide as 15 to 20 nm, but may be sufficient to control the growth of the quantum dots. In the low-contrast method, the resist would be etched in such a way as to form dimples, the shapes of which would mimic the electron-beam density profile. Then by use of a transfer etching process that etches the substrate faster than it etches the resist, either the pattern of holes or a pattern comprising the narrow, lowest portions of the dimples would be imparted to the substrate. Having been thus patterned, the substrate would be cleaned. The resulting holes or dimples in the substrate would serve as nucleation sites for the growth of quantum dots of controlled size in the following steps. The substrate would be cleaned, then placed in a molecular-beam-epitaxy (MBE) chamber, where native oxide would be thermally desorbed and the quantum dots would be grown.

Gunapala, Sarath↗

NASA NTRS2008

Fabricating Nanodots using Lift-Off of a Nanopore Template

A process for fabricating a planar array of dots having characteristic dimensions of the order of several nanometers to several hundred nanometers involves the formation and use of a thin alumina nanopore template on a semiconductor substrate. The dot material is deposited in the nanopores, then the template is lifted off the substrate after the dots have been formed. This process is expected to be a basis for development of other, similar nanofabrication processes for relatively inexpensive mass production of nanometerscale optical, optoelectronic, electronic, and magnetic devices. Alumina nanopore templates are self-organized structures that result from anodization of aluminum under appropriate conditions. Alumina nanopore templates have been regarded as attractive for use in fabricating the devices mentioned above, but prior efforts to use alumina nanopore templates for this purpose have not been successful. One reason for the lack of success is that the aspect ratios (ratios between depth and diameter) of the pores have been too large: large aspect ratios can result in blockage of deposition and/or can prevent successful lift-off. The development of the present process was motivated partly by a requirement to reduce aspect ratios to values (of the order of 10) for which there is little or no blockage of deposition and attempts at lift-off are more likely to be successful. The fabrication process is outlined.

Yang, Eui-Hyeok↗

NASA NTRS1990

InAs/GaAs and InAs doping superlattices

The extension of the optical response of narrow band gap III-V semiconductors into the long wavelength infrared radiation (LWIR) regime for high sensitivity sensor applications is a challenging problem. Recent advances in nipi doped GaAs superlattices, lattice mismatched epitaxy and the heteroepitaxial growth of III-V compound semiconductors on silicon substrates offer a number of opportunities. Researchers describe two different device approaches based on the molecular beam epitaxy (MBE) growth of superlattice materials which are directed to LWIR focal plane array technology. The first of these uses nipi superlattices fabricated in bulk InAs which has been grown on either GaAs or Si substrates. The second is based on the growth of a new pseudomorphic tetragonal phase of InAs on GaAs to create a semimetal/semiconductor superlattice material.

Grunthaner, Frank J.↗

NASA NTRS1991

In-situ integrated processing and characterization of thin films of high temperature superconductors, dielectrics and semiconductors by MOCVD

In this strategy of depositing the basic building blocks of superconductors, semiconductors, and dielectrics having common elements, researchers deposited superconducting films of Y-Ba-Cu-O, semiconductor films of Cu2O, and dielectric films of BaF2 and Y2O3 by metal oxide chemical vapor deposition (MOCVD). By switching source materials entering the chamber, and by using direct writing capability, complex device structures like three terminal hybrid semiconductor/superconductor transistors can be fabricated. The Y-Ba-Cu-O superconducting thin films on BaF2/YSZ substrates show a T(sub c) of 80 K and are textured with most of the grains having their c-axis or a-axis perpendicular to the substrate. Electrical characteristics as well as structural characteristics of superconductors and related materials obtained by x-ray deffraction, electron microscopy, and energy dispersive x-ray analysis are discussed.

Singh, R.↗