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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 163 records · Page 9
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Low-cost, high-efficiency III-V photovoltaics enabled by remote epitaxy through graphene (Final Technical Report)

One of the most important outcomes of this project was that the team developed a method to directly grow graphene layer in wafer-scale on III-V substrates. Conventionally, graphene had to be transferred for remote epitaxy, which has imposed significant challenges in scalability, film quality, and substrate recycling, due to the transfer-related issues. The newly developed method of directly forming 2D layers by Metal-Organic Chemical Vapor Deposition (MOCVD) has realized wafer-scale, defect-free graphene formation for remote epitaxy, which has huge implications not only for solar cells but also in expanding the scalability and the possibility for heterointegration with dissimilar material platforms. Another important outcome was on better understanding of remote epitaxy mechanism. The growth of III-V on graphene is vastly different from directly growing films on III-V substrates, because the surface energy of graphene is very small, meaning that the nucleation density on graphene will be much lower than exposed III-V surfaces. Also, the graphene and the interface properties critically affect remote interaction through graphene. With this obtained knowledge regarding III-V remote epitaxy, we were able to achieve wafer-scale single-crystalline remote epitaxy, 100% exfoliation of the remote epitaxial films, as well as multiple times of GaAs wafer reusability demonstration. The general rule of thumbs found during this project will be a stepping stone for the growth and fabrication of various high-performance devices by remote epitaxy. Lastly, because remote epitaxy and 2DLT offer a pathway to isolate single-crystal membranes from the host wafers, the wafer-scale remote epitaxy processes developed in this project could open up pathways for new functionality and multi-functionality by heterointegration of remote epitaxially formed membranes.

14 SOLAR ENERGY↗
DOE OSTI2026

Identification and mitigation of memory block timing issue in ITk ABCStar during ASIC production

The ABCStar is a mixed-signal front-end readout ASIC for the strips sensor portion of the ATLAS ITk detector being developed as part of the High-Luminosity LHC upgrade. In pre-production testing, a subtle design flaw was uncovered in the ABCStar that was reducing wafer yields in some manufactured lots from the expected 90% to as low as 2%. The root cause was determined to be a timing issue in the logic synthesized to control previously silicon proven memory blocks re-used for this ASIC. The solutions proposed included manufacturing process changes by the wafer foundry, changes to the operating parameters for the ABCStar in the detector, and the possibility that a redesign might be required. The two mitigation efforts were undertaken in parallel, with the process modification route a less desirable solution since already manufactured wafers would need to be scrapped in favour of the new ones. Based on a knowledge of the existing process, and testing done on the worst performing wafers, it was proposed that raising the core operating voltage of the ABCStar from 1.20V to 1.25V could address the timing issue by sufficiently speeding up its transistors. An extensive testing program that included the effects of temperature and radiation expected over the lifetime of the ITk detector was conducted to validate that approach. Those tests and studies proved that even the worst performing wafers would have yields over 80% with the 1.25V core voltage, and neither the modified process nor redesign would be required for ensuring reliable operation of the ITk. Based on testing, a further timing mitigation was implemented to provide an additional margin of reliability by increasing the duty cycle of the clock to the ABCStar. Testing of all ABCStar wafers has been completed and the production of the detector modules using these ASICs is now well underway as a result of the efforts detailed herein.

FOS: Physical sciences↗
DOE OSTI2025

Optimization of edge bead removal (EBR) process to enhance defect reduction in optical lithography

Defect reduction remains a critical objective in the integrated circuit manufacturing process, particularly within the highly re-entrant lithography modules where minimizing defects is crucial. Defects at the wafer edge can contaminate lithography modules and downstream processing equipment, leading to redistribution onto the wafer surface and adversely affecting overall device yield. A persistent challenge in the resist coating process is the formation of resist edge beads, driven by the strong Van der Waals attraction of excess photoresist (PR) to itself and the underlying substrate. The edge bead removal (EBR) process is a standard cleaning step designed to eliminate these edge beads and prevent potential contamination. Here, in this study, we identify the sources of EBR induced defects and additional EBR process encroachment toward edge patterning during the EBR cleaning process. This study provides a comprehensive study aimed at optimizing the EBR cleaning process to effectively eliminate EBR-induced defects, thereby enhancing overall device yield. Specifically, we identify three primary defects induced by the EBR cleaning process: rainbow-type, finger-shaped, and teardrop-type defects. Our experimental study reveals that in addition to EBR rinse time, PR cast time is crucial parameters contributing to the formation of these defects. By properly optimizing the PR cast time and EBR rinse time, we were able to remove nearly 100 % of dense clusters of defects that were easily visible even at low magnification optical microscopy throughout the wafer edge. We observed that shorter PR casting times shows edge defects caused by inefficient EBR process because of insufficient time for PR to fully settle causing superfluous PR to continue flowing toward wafer edge during EBR clearing step, leading to partial removal of PR at the wafer edge and the formation of rainbow defects. Proper optimization of both PR casting time and EBR chemistries dispense time is essential to resolve these defects, ensuring efficient EBR cleaning process and improved overall device yield.

42 ENGINEERING↗
DOE OSTI2021

GaAs Solar Cells Grown on Intentionally-Contaminated GaAs Substrates

III-V solar cells have the best performance of any semiconductor materials, but deposition of these materials relies on high-quality single crystal GaAs wafers for their superior performance. Unfortunately, the cost of these wafers makes these high-efficiency devices only accessible in high-value or niche markets. Here, we explored the effect of growing bulk GaAs crystals with lower purity input materials in order to reduce their cost. We observe that intentional impurities added to the melt before the crystal growth occurs segregate to the top of the boule. Single junction GaAs solar cells grown on wafers made from contaminated boules showed no performance degradation compared to a high-purity control wafer. These results suggest that lower purity Ga and As source materials can be used during crystal growth to reduce the cost of wafers.

41 EE - Solar Energy Technologies Office (EE-4S)↗
DOE OSTI2023

Water production for coffee brewing by electrodeionization

A resin-wafer electrodeionization (RW-EDI) apparatus for purifying water for coffee brewing comprises a cathode; an anode; and multiple porous solid resin wafer exchange units arranged in a stack between the cathode and the anode, and an air distributor adapted and arranged to aerate the water to be purified. Each unit comprises a monovalent cation exchange membrane (CEM), an anion exchange membrane (AEM), and an ion exchange resin wafer between the CEM and the AEM, which is in contact with, and in fluid flow connection with the CEM and AEM. Each resin wafer comprises a cation exchange resin and an anion exchange resin. The units are oriented with the CEM facing the cathode and the AEM facing the anode, with space between the units defining ion concentrate chambers. Bipolar ion exchange membranes separate the anode and cathode from their nearest resin wafer exchange units.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2020

Performance of Al-Mn Transition-Edge Sensor Bolometers in SPT-3G

SPT-3G is a polarization-sensitive receiver, installed on the South Pole Telescope, that measures the anisotropy of the cosmic microwave background (CMB) from degree to arcminute scales. The receiver consists of ten 150-mm-diameter detector wafers, containing a total of similar to 16,000transition-edge sensor (TES) bolometers observing at 95, 150, and 220 GHz. During the 2018-2019 austral summer, one of these detector wafers was replaced by a new wafer fabricated with Al-Mn TESs instead of the Ti/Au design originally deployed for SPT-3G. We present the results of in-laboratory characterization and on-sky performance of this Al-Mn wafer, including electrical and thermal properties, optical efficiency measurements, and noise-equivalent temperature. In addition, we discuss and account for several calibration-related systematic errors that affect measurements made using frequency-domain multiplexing readout electronics.

Al-Mn↗
DOE OSTI2020

Commercially Fabricated Antenna-Coupled Transition Edge Sensor Bolometer Detectors for Next-Generation Cosmic Microwave Background Polarimetry Experiment

We report on the development of commercially fabricated multi-chronic antenna-coupled transition edge sensor (TES) bolometer arrays for cosmic microwave background (CMB) polarimetry experiments. The orders of magnitude increase in detector count for next-generation CMB experiments require a new approach in detector wafer production to increase fabrication throughput. Here, we describe collaborative efforts with a commercial superconductor electronics fabrication facility (SeeQC, Inc.) to fabricate antenna-coupled TES bolometer detectors. We have successfully fabricated an operational dual-polarization, dichroic sinuous antenna-coupled TES detector array on a 150-mm-diameter wafer. The fabricated detector arrays have average yield of 95% and excellent uniformity across the wafer. Both RF characteristics and TES bolometer properties are suitable for CMB observations. We successfully fabricated different types of TES bolometers optimized for frequency multiplexing readout, time-domain multiplexing readout, and microwave SQUID multiplexing readout. We also demonstrated high production throughput. We discuss the motivation, design considerations, fabrication processes, test results, and how industrial detector fabrication could be a path to fabricate hundreds of detector wafers for future CMB polarimetry experiments.

47 OTHER INSTRUMENTATION↗
DOE OSTI2024

Innovative recycling of high purity silver from silicon solar cells by acid leaching and ultrasonication

Precious and scarce silver (Ag) is used as a front electrical contact in silicon solar panels. With massive amounts of solar panel waste coming to end-of-life, it is imperative to recover all the Ag from these modules. In this paper, we propose a novel method to easily reclaim Ag from end-of-life silicon solar cells using low concentration sulfuric acid (H 2 SO 4 ) leaching followed by ultrasonication. Our process simplifies the Ag recycling procedure by directly recovering the Ag contacts from solar cells, eliminating the need for secondary precipitation/electrodeposition. First, scanning electron microscopy (SEM) with energy dispersive X-ray spectroscopy (EDX) and X-ray photoelectron spectroscopy (XPS) was used to study the leaching and ultrasonication process on rejected solar wafers. Next, a solar panel from landfill was heated in a furnace to burn off the polymer encapsulant. The silicon wafers were then collected from the burning process and leached in 2 M H 2 SO 4 at two different shaking speeds for 48 hours at room temperature. Finally, the end-of-life silicon wafer pieces were collected, sonicated in water, and then the sonication water was centrifuged to show a proof-of-concept to recover the Ag contacts. Inductively coupled plasma optical emission spectroscopy (ICPOES) is used to monitor dissolved elements in the leachate as a function of time and shaking speed. XPS is used to evaluate the composition of the silicon cell wafer surface before and after H 2 SO 4 leaching. SEM is used to image the recovered Ag contacts morphology and EDX confirms the recovered particles contain high amounts of Ag. Furthermore, a proposed schematic illustrates the authors’ hypothesis for the peeling mechanism.

14 SOLAR ENERGY↗
DOE OSTI2025

Low embodied energy and carbon, high lifetime silicon boules via a combined chemical vapor deposition/float zone process

This work evaluates a new process route to making float zone (Fz)-quality silicon wafers using a combination of computational fluid dynamics (CFD) modeling and technoeconomic analysis. Our analysis finds that the new process competes with Czochralski (Cz)-grown wafers on a levelized cost of energy system level. The new process also decreases embodied energy and carbon of silicon photovoltaics (PV) by ~6x circumventing the energy-costly Siemens process used in polycrystalline silicon (poly-Si) production plants to generate feedstock for Fz and Cz boules. Instead of using poly-Si from the Siemens process to feed crystallization, the new process uses the high-purity, trichlorosilane (TCS) precursor gas to grow a poly-Si feed rod in-situ during a modified Fz1,2 boule growth process. The gas-to-boule float zone process enables opportunity to produce high-purity (low metals and oxygen content), uniformly doped single crystal silicon boules and wafers with high bulk lifetimes (τ bulk > 15 ms) to enable higher efficiency cells (>27 %) with fewer known degradation mechanisms than Czochralski (Cz)-grown wafers. These benefits reduce the levelized cost of electricity (LCOE) of PV-produced electricity. Here we show the results of our CFD and chemical modeling of the process to prove feasibility and economic viability.

14 SOLAR ENERGY↗
DOE OSTI2024

Continuously tunable uniaxial strain control of van der Waals heterostructure devices

Uniaxial strain has been widely used as a powerful tool for investigating and controlling the properties of quantum materials. However, existing strain techniques have so far mostly been limited to use with bulk crystals. Although recent progress has been made in extending the application of strain to two-dimensional van der Waals (vdW) heterostructures, these techniques have been limited to optical characterization and extremely simple electrical device geometries. Here, we report a piezoelectric-based in situ uniaxial strain technique enabling simultaneous electrical transport and optical spectroscopy characterization of dual-gated vdW heterostructure devices. Critically, our technique remains compatible with vdW heterostructure devices of arbitrary complexity fabricated on conventional silicon/silicon dioxide wafer substrates. We demonstrate a large and continuously tunable strain of up to –0.15% at millikelvin temperatures, with larger strain values also likely achievable. We quantify the strain transmission from the silicon wafer to the vdW heterostructure, and further demonstrate the ability of strain to modify the electronic properties of twisted bilayer graphene. Our technique provides a highly versatile new method for exploring the effect of uniaxial strain on both the electrical and optical properties of vdW heterostructures and can be easily extended to include additional characterization techniques.

Electrical properties and parameters↗
DOE OSTI2021

Sonic Lift-off of GaAs-based Solar Cells with Reduced Surface Facets

Spalling has been proposed as a promising kerfless technique for slicing thin wafers and devices, enhancing the wafer yield from an ingot by reducing kerf-losses and enabling substrate reuse for the case of costly devices. The main challenge of spalling is to control the roughness and thickness variation of the spalled wafers that can be as high as 100% of the wafer thickness. Here, we have shown previously that the thickness variations are largely influenced by the interaction of the crack front with its own reflected waves. Herein we show that through Sonic Lift-off we can offer a modification to standard spalling technologies that minimizes the interaction of reflected waves with the crack front during lift-off of GaAs(100)-based solar cells. We show that the average surface facets amplitude can be reduced by 96% while obtaining a high quality bulk with no discernible residual strain as measured by PL. The resulting spalling depth can easily be tuned from 100 µm to less than 15µm. The electrical characterization of the Sonic lift-off cell shows no degradation of the VOC and a power conversion within 99% relative of a non-spalled baseline.

42 ENGINEERING↗
DOE OSTI2021

Facet Suppression in (100) GaAs Spalling via Use of a Nanoimprint Lithography Release Layer

Controlled spalling is an emerging technique developed for fast, scalable wafer reuse, but for the commonly used (100) GaAs substrate system, the process leaves large facets ranging from 5-10 µm on the wafer surface. Removing them for wafer reuse requires a costly re-polishing step that limits the cost savings that can be achieved with spalling as a wafer reuse technique. In this study, we investigate facet suppression in spalling of (100) GaAs by redirecting the fracture front along features created by buried nanoimprint lithography (NIL)-patterned SiO 2 . We show successful facet suppression using patterns that result in favorable fracture along the SiO 2 /GaAs interface. The results from this work show NIL patterned interlayers are a promising method for faceting suppression in (100) GaAs spalling.

controlled spalling↗
DOE OSTI2022

Fabrication and Irradiation Behavior of Thulium Sesquioxide

The results of reactor irradiation of thulium sesquioxide are discussed, along with chemical and physical properties and wafer fabrication. Sintered densities up to 90% of theoretical were obtained in target wafers using oxide reprocessed to obtain readily sinterable powder. Irradiation to about 1.8 w/g did not change the microstructure of the wafers although some wafers broke, probably because of mechanical stresses in target and disassembly.

36 MATERIALS SCIENCE↗
DOE OSTI2026

A Path to III-V Photovoltaic Cost Reduction Combining GaAs (211) Spalling with Halide Vapor Phase Epitaxy

This presentation is an overview of the following, Spalling on 211 oriented wafers produces flat surface without faceting: 1) Demonstrated spall on entire 2" wafer; 2) GaAs and GaInP grown on 211 wafers by HVPE; and 3) Promising cell with VOC=1.02 V and IQE-1. Next steps: 1) Grow cell on spalled wafer and 2) Growth studies to improve material and cell on 211 substrates.

14 SOLAR ENERGY↗
DOE OSTI2025

Quality assurance and quality control of the $26~\text {m}^2$ SiPM production for the DarkSide-20k dark matter experiment

DarkSide-20k is a novel liquid argon dark matter detector currently under construction at the Laboratori Nazionali del Gran Sasso (LNGS) of the Istituto Nazionale di Fisica Nucleare (INFN) that will push the sensitivity for Weakly Interacting Massive Particle (WIMP) detection into the neutrino fog. The core of the apparatus is a dual-phase Time Projection Chamber (TPC), filled with 50 tonnes of low radioactivity underground argon (UAr) acting as the WIMP target. NUV-HD-cryo Silicon Photomultipliers (SiPM)s designed by Fondazione Bruno Kessler (FBK) (Trento, Italy) were selected as the photon sensors covering two $10.5~\text {m}^2$ Optical Planes, one at each end of the TPC, and a total of $5~\text {m}^2$ photosensitive surface for the liquid argon veto detectors. This paper describes the Quality Assurance and Quality Control (QA/QC) plan and procedures accompanying the production of FBK NUV-HD-cryo SiPM wafers manufactured by LFoundry s.r.l. (Avezzano, AQ, Italy). SiPM characteristics are measured at 77 K at the wafer level with a custom-designed probe station. As of March 2025, 1314 of the 1400 production wafers (94% of the total) for DarkSide-20k were tested. The wafer yield is $93.2\pm 2.5$%, which exceeds the 80% specification defined in the original DarkSide-20k production plan.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

Offset-aligned three-dimensional integrated circuit

A method for manufacturing a three-dimensional integrated circuit includes attaching a first side of a first die to a first carrier wafer. The method includes preparing a second side of the first die to generate a prepared second side of the first die. The method includes attaching the prepared second side of the first die to a second carrier wafer. The method includes removing the first carrier wafer from the first side of the first die to form a transitional three-dimensional integrated circuit. The method includes attaching a third carrier wafer to a first side of the transitional three-dimensional integrated circuit. The method includes attaching a first side of the second die to a second side of the transitional three-dimensional integrated circuit.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

One-Step Transfer of Symmetric and Asymmetric Contacts for Large-Scale 2D Electronics and Optoelectronics

Two-dimensional (2D) semiconductors are highly promising candidates for thin-film transistor applications due to their scalability, transferability, atomic thickness, and relatively high carrier mobility. However, a substantial performance gap remains between individual devices based on single-crystalline 2D films and wafer-scale integrated circuits, primarily due to defects introduced during conventional fabrication processes. Here, we report a diamond-assisted electrode transfer technique for the van der Waals integration of wafer-scale prefabricated electrode arrays onto 2D materials, enabling scalable electronics and optoelectronics. Implemented on metal–organic chemical vapor deposition-grown monolayer molybdenum disulfide, this method forms ultraclean metal–semiconductor interfaces, yielding field-effect transistors with excellent ohmic contacts, a low contact resistance of 400 Ω·μm, and a Schottky barrier height of only 9 meV. Furthermore, we demonstrate a scalable transistor array on monolayer molybdenum disulfide with excellent device performance uniformity, achieving an average field-effect mobility of 30 cm 2 V –1 s –1 and an on/off current ratio exceeding 105. Additionally, high photocurrent and responsivity were demonstrated in the array devices, showing their potential for excellent image detection. We further demonstrate the versatility of this technique by fabricating a Schottky diode array through a single-step transfer of asymmetric electrodes─low work function aluminum and high work function gold─onto monolayer tungsten diselenide. This approach provides a clean, effective solution for contact engineering in 2D materials, offering a viable pathway toward wafer-scale, high-performance 2D electronics, optoelectronics, and integrated circuits.

2D electronics↗
DOE OSTI2019

Two-dimensional ferromagnetic superlattices

Mechanically exfoliated two-dimensional ferromagnetic materials (2D FMs) possess long-range ferromagnetic order and topologically nontrivial skyrmions in few layers. However, because of the dimensionality effect, such few-layer systems usually exhibit much lower Curie temperature (T C ) compared to their bulk counterparts. It is therefore of great interest to explore effective approaches to enhance their T C , particularly in wafer-scale for practical applications. Here, we report an interfacial proximity-induced high-T C 2D FM Fe 3 GeTe 2 (FGT) via A-type antiferromagnetic material CrSb (CS) which strongly couples to FGT. A superlattice structure of (FGT/CS) n , where n stands for the period of FGT/CS heterostructure, has been successfully produced with sharp interfaces by molecular-beam epitaxy on 2-inch wafers. By performing elemental specific X-ray magnetic circular dichroism (XMCD) measurements, we have unequivocally discovered that T C of 4-layer Fe 3 GeTe 2 can be significantly enhanced from 140 K to 230 K because of the interfacial ferromagnetic coupling. Meanwhile, an inverse proximity effect occurs in the FGT/CS interface, driving the interfacial antiferromagnetic CrSb into a ferrimagnetic state as evidenced by double-switching behavior in hysteresis loops and the XMCD spectra. Density functional theory calculations show that the Fe-Te/Cr-Sb interface is strongly FM coupled and doping of the spin-polarized electrons by the interfacial Cr layer gives rise to the T C enhancement of the Fe 3 GeTe 2 films, in accordance with our XMCD measurements. Strikingly, by introducing rich Fe in a 4-layer FGT/CS superlattice, T C can be further enhanced to near room temperature. Our results provide a feasible approach for enhancing the magnetic order of few-layer 2D FMs in wafer-scale and render opportunities for realizing realistic ultra-thin spintronic devices.

(Fe3GeTe2/CrSb)n superlattice↗