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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 163 records · Page 9

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NASA NTRS1990

Analog Delta-Back-Propagation Neural-Network Circuitry

Changes in synapse weights due to circuit drifts suppressed. Proposed fully parallel analog version of electronic neural-network processor based on delta-back-propagation algorithm. Processor able to "learn" when provided with suitable combinations of inputs and enforced outputs. Includes programmable resistive memory elements (corresponding to synapses), conductances (synapse weights) adjusted during learning. Buffer amplifiers, summing circuits, and sample-and-hold circuits arranged in layers of electronic neurons in accordance with delta-back-propagation algorithm.

Eberhart, Silvio↗

NASA NTRS1996

Shape-Memory-Alloy-Based Deicing System Developed

Ice buildup on aircraft leading edge surfaces has historically been a problem. Most conventional deicing systems rely either on surface heating to melt the accreted ice or pneumatic surface inflation to mechanically debond the ice. Deicers that rely solely on surface heating require large amounts of power. Pneumatic deicers usually cannot remove thin layers of ice and lack durability. Thus, there is a need for an advanced, low-power ice protection system. As part of the NASA Small Business and Innovation Research (SBIR) program, Innovative Dynamics, Inc., developed an aircraft deicing system that utilizes the properties of Shape Memory Alloys (SMA). The SMA-based system has achieved promising improvements in energy efficiency and durability over more conventional deicers. When they are thermally activated, SMA materials change shape; this is analogous to a conventional thermal expansion. The thermal input is currently applied via conventional technology, but there are plans to implement a passive thermal input that is supplied from the energy transfer due to the formation of the ice itself. The actively powered deicer was tested in the NASA Lewis Icing Research Tunnel on a powered rotating rig in early 1995. The system showed promise, deicing both rime and glaze ice shapes as thin as 1/8 in. The first prototype SMA deicer reduced power usage by 45 percent over existing electrothermal systems. This prototype system was targeted for rotorcraft system development. However, there are current plans underway to develop a fixed-wing version of the deicer.

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NASA NTRS1975

Recent advances in strapdown inertial navigation

The computational requirements and basic features of strapdown gyroscopes for inertial navigation are discussed. Strapdown navigators currently require 20 to 50% of the available time of a minicomputer with a capability of several hundred thousand operations per second; memory requirements are 2000 to 3000 16-bit words. A system in which these computational demands are met by three limited capability microcomputers is described. A technique using dedicated microprocessors in the place of analog electronics in the gyroscope control loops is discussed, and attention is given to applications of microprocessor technology in redundant strapdown navigation systems and associated flight control systems.

Napjus, G. A.↗

NASA NTRS2005

Astrobiology and the Basaltic Plains in Gusev Crater

This report assesses the availability of nutrient elements, energy and liquid water on the plains surrounding Columbia Memorial Station by evaluating observations by the MER rover Spirit in the context of previous Mars missions, Earth-based studies of martian meteorites and studies of microbial communities on Earth that represent potential analogs of martian biota.

DesMarais, D. J.↗

NASA NTRS2002

Rapid evolution of analog circuits configured on a field programmable transistor array

The purpose of this paper is to illustrate evolution of analog circuits on a stand-alone board-level evolvable system (SABLES). SABLES is part of an effort to achieve integrated evolvable systems. SABLES provides autonomous, fast (tens to hundreds of seconds), on-chip circuit evolution involving about 100,000 circuit evaluations. Its main components are a JPL Field Programmable Transistor Array (FPTA) chip used as transistor-level reconfigurable hardware, and a TI DSP that implements the evolutionary algorithm controlling the FPTA reconfiguration. The paper details an example of evolution on SABLES and points out to certain transient and memory effects that affect the stability of solutions obtained reusing the same piece of hardware for rapid testing of individuals during evolution.

SABLES analog circuits field programmable transist↗

NASA NTRS1986

Digital Signal Combining for Conference Calling

Signals combined with minimal noise by use of sums in read-only memories. Signals from subscribers A and B digitized, transmitted, and combined by addressing ROM. Combining operation electronic equivalent of looking up value of function of two variables in mathematical table. Combined digitized signal transmitted, converted to analog form, and delivered to subscriber C. System intended especially for combining number of separate audio signals into one signal for retransmission, as in telephone conference calling.

Byrne, F.↗

NASA NTRS2008

Reconfigurable HIL Testing of Earth Satellites

In recent years, hardware-in-the-loop (HIL) testing has carved a strong niche in several industries, such as automotive, aerospace, telecomm, and consumer electronics. As desktop computers have realized gains in speed, memory size, and data storage capacity, hardware/software platforms have evolved into high performance, deterministic HIL platforms, capable of hosting the most demanding applications for testing components and subsystems. Using simulation software to emulate the digital and analog I/O signals of system components, engineers of all disciplines can now test new systems in realistic environments to evaluate their function and performance prior to field deployment. Within the Aerospace industry, space-borne satellite systems are arguably some of the most demanding in terms of their requirement for custom engineering and testing. Typically, spacecraft are built one or few at a time to fulfill a space science or defense mission. In contrast to other industries that can amortize the cost of HIL systems over thousands, even millions of units, spacecraft HIL systems have been built as one-of-a-kind solutions, expensive in terms of schedule, cost, and risk, to assure satellite and spacecraft systems reliability. The focus of this paper is to present a new approach to HIL testing for spacecraft systems that takes advantage of a highly flexible hardware/software architecture based on National Instruments PXI reconfigurable hardware and virtual instruments developed using LabVIEW. This new approach to HIL is based on a multistage/multimode spacecraft bus emulation development model called Reconfigurable Hardware In-the-Loop or RHIL.

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NASA NTRS1992

System for memorizing maximum values

The invention discloses a system capable of memorizing maximum sensed values. The system includes conditioning circuitry which receives the analog output signal from a sensor transducer. The conditioning circuitry rectifies and filters the analog signal and provides an input signal to a digital driver, which may be either linear or logarithmic. The driver converts the analog signal to discrete digital values, which in turn triggers an output signal on one of a plurality of driver output lines n. The particular output lines selected is dependent on the converted digital value. A microfuse memory device connects across the driver output lines, with n segments. Each segment is associated with one driver output line, and includes a microfuse that is blown when a signal appears on the associated driver output line.

Bozeman, Richard J., Jr.↗

NASA NTRS1996

System for Memorizing Maximum Values

The invention discloses a system capable of memorizing maximum sensed values. The system includes conditioning circuitry which receives the analog output signal from a sensor transducer. The conditioning circuitry rectifies and filters the analog signal and provides an input signal to a digital driver, which may be either liner or logarithmic. The driver converts the analog signal to discrete digital values, which in turn triggers an output signal on one of a plurality of driver output lines n. The particular output lines selected is dependent on the converted digital value. A microfuse memory device connects across the driver output lines, with n segments. Each segment is associated with one driver output line, and includes a microfuse that is blown when a signal appears on the associated driver output line.

Bozeman, Richard J., Jr.↗

NASA NTRS2013

SpaceCube Version 1.5

SpaceCube 1.5 is a high-performance and low-power system in a compact form factor. It is a hybrid processing system consisting of CPU (central processing unit), FPGA (field-programmable gate array), and DSP (digital signal processor) processing elements. The primary processing engine is the Virtex- 5 FX100T FPGA, which has two embedded processors. The SpaceCube 1.5 System was a bridge to the SpaceCube 2.0 and SpaceCube 2.0 Mini processing systems. The SpaceCube 1.5 system was the primary avionics in the successful SMART (Small Rocket/Spacecraft Technology) Sounding Rocket mission that was launched in the summer of 2011. For SMART and similar missions, an avionics processor is required that is reconfigurable, has high processing capability, has multi-gigabit interfaces, is low power, and comes in a rugged/compact form factor. The original SpaceCube 1.0 met a number of the criteria, but did not possess the multi-gigabit interfaces that were required and is a higher-cost system. The SpaceCube 1.5 was designed with those mission requirements in mind. The SpaceCube 1.5 features one Xilinx Virtex-5 FX100T FPGA and has excellent size, weight, and power characteristics [4×4×3 in. (approx. = 10×10×8 cm), 3 lb (approx. = 1.4 kg), and 5 to 15 W depending on the application]. The estimated computing power of the two PowerPC 440s in the Virtex-5 FPGA is 1100 DMIPS each. The SpaceCube 1.5 includes two Gigabit Ethernet (1 Gbps) interfaces as well as two SATA-I/II interfaces (1.5 to 3.0 Gbps) for recording to data drives. The SpaceCube 1.5 also features DDR2 SDRAM (double data rate synchronous dynamic random access memory); 4- Gbit Flash for storing application code for the CPU, FPGA, and DSP processing elements; and a Xilinx Platform Flash XL to store FPGA configuration files or application code. The system also incorporates a 12 bit analog to digital converter with the ability to read 32 discrete analog sensor inputs. The SpaceCube 1.5 design also has a built-in accelerometer. In addition, the system has 12 receive and transmit RS- 422 interfaces for legacy support. The SpaceCube 1.5 processor card represents the first NASA Goddard design in a compact form factor featuring the Xilinx Virtex- 5. The SpaceCube 1.5 incorporates backward compatibility with the Space- Cube 1.0 form factor and stackable architecture. It also makes use of low-cost commercial parts, but is designed for operation in harsh environments.

Geist, Alessandro↗

NASA NTRS1982

Beyond the supercomputer

A NASA-directed development of massively parallel processor (MPP) computers is outlined, noting intended applications for data processing for near term earth resource and environment mapping, radar, and television transmissions. The MPP is designed to perform 100 billion operations/sec to obtain satisfactory image processing, while separate processing units correct distortions, register images, calculate correlation functions, and classify multispectral characteristics. Arrays of 1s and 0s will be manipulated in analog-to-digital conversions generating separate planes corresponding to powers of binaries. Data wires are replaced by fiber-optic tubes or thousands of wires, and single logic gates are replaced by thousands of logic gates and every memory element by thousands of memory elements. Features of the interconnections and the images control processor units are detailed, along with implementation of sliders for program flexibility.

Schaefer, D. H.↗

NASA NTRS1994

Evidence that the protocell was also a protoneuron

A blueprint for a protocell was presented in 1960 (Fox) as a consequence of the newly discovered self-ordering of amino acids and the self-organization of the resultant thermal proteins into cellular structures. The biofunctions of the laboratory protocells (proteinoid microspheres) have since been cataloged; they display roots of many phenomena of modern cells, e.g. synthesis of internucleotide and peptide bonds in aqueous media. These results are inconsistent with a popular assumption that DNA/RNA preceded protein in earliest molecular evolution. The necessity for synthetic research on molecules and cells to 'begin at the beginning' is being realized. Ivanov and Fortsch (1986) have described by analysis how the self-ordering mechanism of amino acids into informed thermal proteins was conserved in evolution from the earliest stage as modern (reverse) mechanisms assumed control. Tyagi and Ponnamperuma (1990) have negated assumptions corollary to DNA/RNA. Ponnamperuma has demonstrated the powerful effect of self-ordering of amino acids in polymerization of aminoacyl nucleotides and the irrelevance of mononucleotide residues. Excitable thermal proteins (Vaughan et al, 1987) are neurotrophic and antiaging when added to cultures of real neurons (Hefti et al, 1991) and are memory enhancers in mice (Fox and Flood, 1992). Proteinoid microspheres of dominant hydrophobic constitution form 'gap junctions', sprout axon-like outgrowths, and form dendritic networks spontaneously. In the latest studies, phenylalanine-rich equimolar proteinoid or the leucine analog (Ishima et al 1981), is found to produce electrical signals for several days when lecithin is included in the assembly with the thermal polymer.

Bi, YU↗

NASA NTRS1982

Two-Stage Linearization Circuit

High accuracy is obtained by combining analog and digital corrections. Proximity-sensor linearization circuit has two stages. First-stage linearization is accurate to about 3 percent; accuracy of final output is better than 0.5 percent. By modifying contents of the Programable Read-Only Memory (PROM), circuit can also be used to derive a nonlinear output.

Waldeck, G. C.↗

NASA NTRS2011

S-Band POSIX Device Drivers for RTEMS

This is a set of POSIX device driver level abstractions in the RTEMS RTOS (Real-Time Executive for Multiprocessor Systems real-time operating system) to SBand radio hardware devices that have been instantiated in an FPGA (field-programmable gate array). These include A/D (analog-to-digital) sample capture, D/A (digital-to-analog) sample playback, PLL (phase-locked-loop) tuning, and PWM (pulse-width-modulation)-controlled gain. This software interfaces to Sband radio hardware in an attached Xilinx Virtex-2 FPGA. It uses plug-and-play device discovery to map memory to device IDs. Instead of interacting with hardware devices directly, using direct-memory mapped access at the application level, this driver provides an application programming interface (API) offering that easily uses standard POSIX function calls. This simplifies application programming, enables portability, and offers an additional level of protection to the hardware. There are three separate device drivers included in this package: sband_device (ADC capture and DAC playback), pll_device (RF front end PLL tuning), and pwm_device (RF front end AGC control).

Lux, James P.↗

NASA NTRS1984

Data reduction programs for a laser radar system

The listing and description of software routines which were used to analyze the analog data obtained from LIDAR - system are given. All routines are written in FORTRAN - IV on a HP - 1000/F minicomputer which serves as the heart of the data acquisition system for the LIDAR program. This particular system has 128 kilobytes of highspeed memory and is equipped with a Vector Instruction Set (VIS) firmware package, which is used in all the routines, to handle quick execution of different long loops. The system handles floating point arithmetic in hardware in order to enhance the speed of execution. This computer is a 2177 C/F series version of HP - 1000 RTE-IVB data acquisition computer system which is designed for real time data capture/analysis and disk/tape mass storage environment.

Badavi, F. F.↗

NASA NTRS1997

Development of Improved Surface Integral Methods for Jet Aeroacoustic Predictions

The accurate prediction of aerodynamically generated noise has become an important goal over the past decade. Aeroacoustics must now be an integral part of the aircraft design process. The direct calculation of aerodynamically generated noise with CFD-like algorithms is plausible. However, large computer time and memory requirements often make these predictions impractical. It is therefore necessary to separate the aeroacoustics problem into two parts, one in which aerodynamic sound sources are determined, and another in which the propagating sound is calculated. This idea is applied in acoustic analogy methods. However, in the acoustic analogy, the determination of far-field sound requires the solution of a volume integral. This volume integration again leads to impractical computer requirements. An alternative to the volume integrations can be found in the Kirchhoff method. In this method, Green's theorem for the linear wave equation is used to determine sound propagation based on quantities on a surface surrounding the source region. The change from volume to surface integrals represents a tremendous savings in the computer resources required for an accurate prediction. This work is concerned with the development of enhancements of the Kirchhoff method for use in a wide variety of aeroacoustics problems. This enhanced method, the modified Kirchhoff method, is shown to be a Green's function solution of Lighthill's equation. It is also shown rigorously to be identical to the methods of Ffowcs Williams and Hawkings. This allows for development of versatile computer codes which can easily alternate between the different Kirchhoff and Ffowcs Williams-Hawkings formulations, using the most appropriate method for the problem at hand. The modified Kirchhoff method is developed primarily for use in jet aeroacoustics predictions. Applications of the method are shown for two dimensional and three dimensional jet flows. Additionally, the enhancements are generalized so that they may be used in any aeroacoustics problem.

Pilon, Anthony R.↗

NASA NTRS1973

The control of a manipulator by a computer model of the cerebellum.

Extension of previous work by Albus (1971, 1972) on the theory of cerebellar function to an application of a computer model of the cerebellum to manipulator control. Following a discussion of the cerebellar function and of a perceptron analogy of the cerebellum, particularly in regard to learning, an electromechanical model of the cerebellum is considered in the form of an IBM 1800 computer connected to a Rancho Los Amigos arm with seven degrees of freedom. It is shown that the computer memory makes it possible to train the arm on some representative sample of the universe of possible states and to achieve satisfactory performance.

Albus, J. S.↗

NASA NTRS2007

High-Performance, Radiation-Hardened Electronics for Space Environments

The Radiation Hardened Electronics for Space Environments (RHESE) project endeavors to advance the current state-of-the-art in high-performance, radiation-hardened electronics and processors, ensuring successful performance of space systems required to operate within extreme radiation and temperature environments. Because RHESE is a project within the Exploration Technology Development Program (ETDP), RHESE's primary customers will be the human and robotic missions being developed by NASA's Exploration Systems Mission Directorate (ESMD) in partial fulfillment of the Vision for Space Exploration. Benefits are also anticipated for NASA's science missions to planetary and deep-space destinations. As a technology development effort, RHESE provides a broad-scoped, full spectrum of approaches to environmentally harden space electronics, including new materials, advanced design processes, reconfigurable hardware techniques, and software modeling of the radiation environment. The RHESE sub-project tasks are: SelfReconfigurable Electronics for Extreme Environments, Radiation Effects Predictive Modeling, Radiation Hardened Memory, Single Event Effects (SEE) Immune Reconfigurable Field Programmable Gate Array (FPGA) (SIRF), Radiation Hardening by Software, Radiation Hardened High Performance Processors (HPP), Reconfigurable Computing, Low Temperature Tolerant MEMS by Design, and Silicon-Germanium (SiGe) Integrated Electronics for Extreme Environments. These nine sub-project tasks are managed by technical leads as located across five different NASA field centers, including Ames Research Center, Goddard Space Flight Center, the Jet Propulsion Laboratory, Langley Research Center, and Marshall Space Flight Center. The overall RHESE integrated project management responsibility resides with NASA's Marshall Space Flight Center (MSFC). Initial technology development emphasis within RHESE focuses on the hardening of Field Programmable Gate Arrays (FPGA)s and Field Programmable Analog Arrays (FPAA)s for use in reconfigurable architectures. As these component/chip level technologies mature, the RHESE project emphasis shifts to focus on efforts encompassing total processor hardening techniques and board-level electronic reconfiguration techniques featuring spare and interface modularity. This phased approach to distributing emphasis between technology developments provides hardened FPGA/FPAAs for early mission infusion, then migrates to hardened, board-level, high speed processors with associated memory elements and high density storage for the longer duration missions encountered for Lunar Outpost and Mars Exploration occurring later in the Constellation schedule.

Keys, Andrew S.↗