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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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This paper presents an adaptive estimation algorithm for bit synchronization, assuming that the parameters of the incoming data process are time-varying. Experiment results have proved that this synchronizer is workable either judged by the amount of data required or the speed of convergence.
A recursive procedure is derived for decoding of rate R=1/n binary convolutional codes which minimizes the probability of the individual decoding decisions for each information bit subject to the constraint that the decoding delay be limited to Delta branches. This new decoding algorithm is similar to, but somewhat more complex than, the Viterbi decoding algorithm. A real-time, i.e. fixed decoding delay, version of the Viterbi algorithm is also developed and used for comparison to the new algorithm on simulated channels. It is shown that the new algorithm offers advantages over Viterbi decoding in soft-decision applications such as in the inner coding system for concatenated coding.
A recursive procedure is derived for decoding of rate R = 1/n binary convolutional codes which minimizes the probability of the individual decoding decisions for each information bit, subject to the constraint that the decoding delay be limited to Delta branches. This new decoding algorithm is similar to, but somewhat more complex than, the Viterbi decoding algorithm. A real-time, i.e., fixed decoding delay, version of the Viterbi algorithm is also developed and used for comparison to the new algorithm on simulated channels. It is shown that the new algorithm offers advantages over Viterbi decoding in soft-decision applications, such as in the inner coding system for concatenated coding.
This report documents the analysis and experimental validation of the performance of various aspects of a high rate bit synchronizer.
This paper considers bit synchronization through the use of a separate clock signal which is either amplitude modulated onto or summed with the data signal. For continuous data transmission, such schemes are known to be inferior, in the sense of efficient use of power, to schemes which derive synchronization directly from the data signal. However, these techniques have application in burst systems such as spacecraft command systems, and in systems where receiver simplicity is more important than power conservation. For systems in which the composite data-clock signal subsequently modulates an RF carrier, it is shown that the summed clock signal performs slightly better than the AM clock signal, and that for both signal types, the optimum allocation of power between data and clock is approximately 9:1.
Two highly reliable codes termed "Modified b-adjacent interleaving codes" provide fail-safe operation of launch processing and control system in which common memory is coordination point for interconnection of up to 64 minicomputers. Codes detect and correct bit errors in computer data transmission.
Modular interface unit transfers data at high speeds along four channels. Device expedites variable-word-length communication between computers. Operation eases exchange of bit information by automatically reformatting coded input data and status information to match requirements of output.
Twenty-five Hughes HCMP 1852D and 25 RCA CDP1852D 8-bit, CMOS, I/O port microcircuits underwent electrical characterization tests. All electrical measurements were performed on a Tektronix S-3260 Test System. Before electrical testing, the devices were subjected to a 168-hour burn-in at 125 C with the inputs biased at 10V. Four of the Hughes parts became inoperable during testing. They exhibited functional failures and out-of-range parametric measurements after a few runs of the test program.
Performance data taken on several candidate high data rate laser communications photodetectors is presented. Measurements of bit error rate versus signal level were made in both a 1064 nm system at 400 Mbps and a 532 nm system at 500 Mbps. RCA silicon avalanche photodiodes are superior at 1064 nm, but the Rockwell hybrid 3-5 avalanche photodiode preamplifiers offer potentially superior performance. Varian dynamic crossed field photomultipliers are superior at 532 nm, however, the RCA silicon avalanche photodiode is a close contender.
A 36 bit time code generator implemented in CMOS is described. A microprocessor is used to minimize chip count. A modified 20 second format is available as an option, by changing two program steps.
Interpolation techniques for three types (univariate, bivariate, and map) of nonanalytic functions are described. These interpolation techniques are then implemented in scaled fraction arithmetic on a representative 16 bit microprocessor. A FORTRAN program is described that facilitates the scaling, documentation, and organization of data for use by these routines. Listings of all these programs are included in an appendix.
A multiple chip magnetic bubble memory cell design developed for NASA embodies the low power, low weight, environmental tolerance and reliability necessary for successful operation in spacecraft launch and mission environments. Packaging of multiple chips in a common magnetic bias, drive coil assembly reduces weight and volume overhead per chip and also reduces the number of coil drive components required. This 8 x 10 to the 5th bit cell is conduction cooled and provides a metal and ceramic sealed hermetic chip environment.
A 12 bit successive approximation analog to digital converter that offers moderately high speed precision data conversion at a reasonable level of cost and complexity is studied. The ADCH10HT extends this capability over a temperature range of -55 to +200 C. No missing-code performance is maintained over the entire temperature range. The converter is completely self-contained with internal clock and +10 volt reference. The CMOS devices offer low power dissipation, so that the internal temperature of the hybrid circuit does not rise as much from self heating. In CMOS circuits, pn junction leakage currents are returned to the supplies so that the logic keeps working at temperatures up to 250 C.
The various methods of high bit transition density encoding are presented, their relative performance is compared in so far as error propagation characteristics, transition properties and system constraints are concerned. A computer simulation of the system using the specific PN code recommended, is included.
Realization of a bit-serial multiplication algorithm for the encoding of Reed-Solomon (RS) codes on a single VLSI chip using NMOS technology is demonstrated to be feasible. A dual basis (255, 223) over a Galois field is used. The conventional RS encoder for long codes ofter requires look-up tables to perform the multiplication of two field elements. Berlekamp's algorithm requires only shifting and exclusive-OR operations.
Statistical studies of telemetry errors were made on data from the Solar Mesosphere Explorer (SME). Examination of frame sync words, as received at the ground station, indicated a wide spread of Bit Error Rates (BER) among stations. A study of the distribution of errors per station pass, however, showed that there was a tendency for the station software to add an even number of spurious errors to the count. A count of wild points in science data, rejecting drop-outs and other system errors, yielded an average random BER of 3.1 x 10 to the -6 with 99% confidence limits of 2.6 and 3.8 x 10 to the -6. The system errors are typically 5 to 100 times more frequent than the truly random errors.
This paper investigates bandwidth compression of delta modulated video signals using a variety of novel techniques. The video signal is encoded at 16 MHz with an adaptive delta modulator (ADM) using the Song video mode algorithm. One method of achieving bandwidth compression is through the detection and reduction of steady state patterns in the DM bit stream. Further reduction is obtained by deleting the horizontal and vertical drive information. Finally, a modified ADM algorithm is introduced to increase the frequency of steady state patterns. When the modified ADM is combined with entropy coding a 30-50% data compression can be realized.
The use of PN sequence generators to create a minimum number of transitions in an NRZ bit stream is described. The CSG encoder/decoder design was constructed and demonstrated.