Search NASASearch

SEARCH · Search NASA

Results for “code generation”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 163 records · Page 9

Kinetic modeling of hot tail runaway electron generation during plasma disruptions using the JOREK code

The generation of runaway electrons (REs) during disruptions poses a significant challenge for the operation of tokamaks. The production of these high-energy electrons can cause substantial damage, particularly when the plasma current is high, making it a critical concern for ITER. For the high-temperature plasmas anticipated in ITER, the primary generation of REs may be dominated by the hot tail mechanism, which consists of the acceleration of hot electrons from the pre-disruption population which have not yet thermalized with the bulk following the rapid cooling of the plasma. To account for the significant 3D effects on RE production, a hot tail modeling framework has been developed within the non-linear 3D extended MHD code JOREK. This paper presents the structure of this framework, which is based on test electrons evolving in MHD fields. The verification of the method shows good agreement with the reference DREAM code for 0D test cases, as well as for axisymmetric simulations of 15 MA ITER H-mode disruption scenarios. Furthermore, a proof-of-principle application to a DIII-D case demonstrates the framework’s capability to capture for the first time the hot tail generation in 3D MHD simulations in realistic geometry. Preliminary results suggest that the production of REs is significantly reduced by stochastic losses.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY

Performance Bounds on Two Concatenated, Interleaved Codes

A method has been developed of computing bounds on the performance of a code comprised of two linear binary codes generated by two encoders serially concatenated through an interleaver. Originally intended for use in evaluating the performances of some codes proposed for deep-space communication links, the method can also be used in evaluating the performances of short-block-length codes in other applications. The method applies, more specifically, to a communication system in which following processes take place: At the transmitter, the original binary information that one seeks to transmit is first processed by an encoder into an outer code (Co) characterized by, among other things, a pair of numbers (n,k), where n (n > k)is the total number of code bits associated with k information bits and n k bits are used for correcting or at least detecting errors. Next, the outer code is processed through either a block or a convolutional interleaver. In the block interleaver, the words of the outer code are processed in blocks of I words. In the convolutional interleaver, the interleaving operation is performed bit-wise in N rows with delays that are multiples of B bits. The output of the interleaver is processed through a second encoder to obtain an inner code (Ci) characterized by (ni,ki). The output of the inner code is transmitted over an additive-white-Gaussian- noise channel characterized by a symbol signal-to-noise ratio (SNR) Es/No and a bit SNR Eb/No. At the receiver, an inner decoder generates estimates of bits. Depending on whether a block or a convolutional interleaver is used at the transmitter, the sequence of estimated bits is processed through a block or a convolutional de-interleaver, respectively, to obtain estimates of code words. Then the estimates of the code words are processed through an outer decoder, which generates estimates of the original information along with flags indicating which estimates are presumed to be correct and which are found to be erroneous. From the perspective of the present method, the topic of major interest is the performance of the communication system as quantified in the word-error rate and the undetected-error rate as functions of the SNRs and the total latency of the interleaver and inner code. The method is embodied in equations that describe bounds on these functions. Throughout the derivation of the equations that embody the method, it is assumed that the decoder for the outer code corrects any error pattern of t or fewer errors, detects any error pattern of s or fewer errors, may detect some error patterns of more than s errors, and does not correct any patterns of more than t errors. Because a mathematically complete description of the equations that embody the method and of the derivation of the equations would greatly exceed the space available for this article, it must suffice to summarize by reporting that the derivation includes consideration of several complex issues, including relationships between latency and memory requirements for block and convolutional codes, burst error statistics, enumeration of error-event intersections, and effects of different interleaving depths. In a demonstration, the method was used to calculate bounds on the performances of several communication systems, each based on serial concatenation of a (63,56) expurgated Hamming code with a convolutional inner code through a convolutional interleaver. The bounds calculated by use of the method were compared with results of numerical simulations of performances of the systems to show the regions where the bounds are tight (see figure).

Moision, Bruce

Lock detector for noise-coded signals

Circuit indicates when receiver is locked on pseudorandom-noise-coded signal. Circuit is used for reception of such digitally coded signals as scrambled voice messages or scrambled video. Circuit determines when receiver generated code is correct and synchronized with incoming signal so that receiver can track signal.

Carson, L. M.

Further Results On Finite-State Codes

New codes generated and analyzed. Report discusses application of general construction for finite-state (FS) codes to known block codes. Decoding algorithms and results of simulations discussed briefly. First, general construction applied to (24,12) Golay code. Next, general construction applied to (16,8) Nordstrom-Robinson code. Results presented as plots of bit-error probability versus ratio of bit energy to noise energy.

Pollara, F.

Finding the complete path and weight enumerators of convolutional codes

A method for obtaining the complete path enumerator T(D, L, I) of a convolutional code is described. A system of algebraic equations is solved, using a new algorithm for computing determinants, to obtain T(D, L, I) for the (7,1/2) NASA standard code. Generating functions, derived from T(D, L, I) are used to upper bound Viterbi decoder error rates. This technique is currently feasible for constraint length K less than 10 codes. A practical, fast algorithm is presented for computing the leading nonzero coefficients of the generating functions used to bound the performance of constraint length K less than 20 codes. Code profiles with about 50 nonzero coefficients are obtained with this algorithm for the experimental K = 15, rate 1/4, code in the Galileo mission and for the proposed K = 15, rate 1/6, 2-dB code.

Onyszchuk, I.

Systems, methods and apparatus for generation and verification of policies in autonomic computing systems

Described herein is a method that produces fully (mathematically) tractable development of policies for autonomic systems from requirements through to code generation. This method is illustrated through an example showing how user formulated policies can be translated into a formal mode which can then be converted to code. The requirements-based programming method described provides faster, higher quality development and maintenance of autonomic systems based on user formulation of policies.Further, the systems, methods and apparatus described herein provide a way of analyzing policies for autonomic systems and facilities the generation of provably correct implementations automatically, which in turn provides reduced development time, reduced testing requirements, guarantees of correctness of the implementation with respect to the policies specified at the outset, and provides a higher degree of confidence that the policies are both complete and reasonable. The ability to specify the policy for the management of a system and then automatically generate an equivalent implementation greatly improves the quality of software, the survivability of future missions, in particular when the system will operate untended in very remote environments, and greatly reduces development lead times and costs.

Hinchey, Michael G.

Four-Cylinder Stirling-Engine Computer Program

Computer program developed for simulating steady-state and transient performance of four-cylinder Stirling engine. In model, four cylinders interconnected by four working spaces. Each working space contains seven volumes: one for expansion space, heater, cooler, and compression space and three for regenerator. Thermal time constant for regenerator mass associated with each regenator gas volume. Former code generates results very quickly, since it has only 14 state variables with no energy equation. Current code then used to study various aspects of Stirling engine in much more detail. Program written in FORTRAN IV for use on IBM 370 computer.

Daniele, C. J.

Fatigue and Damage Tolerance Analysis of a Hybrid Composite Tapered Flexbeam

The behavior of nonlinear tapered composite flexbeams under combined axial tension and cyclic bending loading was studied using coupon test specimens and finite element (FE) analyses. The flexbeams used a hybrid material system of graphite/epoxy and glass/epoxy and had internal dropped plies, dropped in an overlapping stepwise pattern. Two material configurations, differing only in the use of glass or graphite plies in the continuous plies near the midplane, were studied. Test specimens were cut from a full-size helicopter tail-rotor flexbeam and were tested in a hydraulic load frame under combined constant axialtension load and transverse cyclic bending loads. The first determination damage observed in the specimens occurred at the area around the tip of the outermost ply-drop group in the tapered region of the flexbeam, near the thick end. Delaminations grew slowly and stably, toward the thick end of the flexbeam, at the interfaces above and below the dropped-ply region. A 2D finite element model of the flexbeam was developed. The model was analyzed using a geometrically non-linear analysis with both the ANSYS and ABAQUS FE codes. The global responses of each analysis agreed well with the test results. The ANSYS model was used to calculate strain energy release rates (G) for delaminations initiating at two different ply-ending locations. The results showed that delaminations were more inclined to grow at the locations where they were observed in the test specimens. Both ANSYS and ABAQUS were used to calculate G values associated with delamination initiating at the observed location but growing in different interfaces, either above or below the ply-ending group toward the thick end, or toward the thin end from the tip of the resin pocket. The different analysis codes generated the same trends and comparable peak values, within 5-11 % for each delamination path. Both codes showed that delamination toward the thick region was largely mode II, and toward the thin region was predominantly mode I. The calculated peak G-values from either analysis predict delamination is most likely to occur along the same interface where it was observed in the test specimens. Calculated peak G values were used with material characterization data to calculate a curve relating the fatigue life of the specimens, N, to the applied transverse load, V, for a given constant axial load.

Murri, Gretchen B.

Verification of the ENDF/B-VII.1 Based MC 2 -3 Library Rev.1

The MC 2 -3 code, developed by Argonne National Laboratory under the DOE-NE NEAMS program, is a multigroup cross section generation code for fast reactor applications. Last year, the ENDF/B-VII.0 (E70) MC 2 -3 library, which has been extensively used, verified, and validated over a long period, was intensively reverified and updated to support the commercial grade dedication (CGD) requirement of the TerraPower Natrium project. This year, the ENDF/B-VII.1 (E71) MC 2 -3 library, the preliminary version of which was generated several years ago, was regenerated and rigorously verified to support the Natrium project as well as the completion of verification of the E71 library. The E71 library was verified using the process developed during the verification of the E70 library, including comparisons of cross sections with the NJOY-generated cross sections, comparisons of the resolved resonance cross sections with those using the PEDNF library, and comparison of total cross sections with the sum of partial cross sections. Additional verifications were conducted to ensure that the benchmark problem solutions with the E71 library are reasonable compared to the corresponding Monte Carlo solutions. Furthermore, the E71 gamma library was generated, which includes data for prompt gamma, delayed gamma, and delayed beta as well as neutron and gamma heating. The gamma library was verified at the level of individual isotopes. The EBR-II core solutions from MC 2 -3/ DIF3D and MCNP were compared, demonstrating that those solutions in terms of k-effective and assembly powers were in good agreement.

22 GENERAL STUDIES OF NUCLEAR REACTORS

Design approach for a microprocessor-based GPS time transfer receiver

The design concept and characteristics of a self-contained microprocessor-based Global Positioning System time transfer receiver is described. A prototype of this unit is currently in the test phase. It employs two-bit digital baseband correlation rather than analog IF correlation of the signals with the reference code. The correlator, numerically controlled oscillators and code generator are implemented in a special-purpose digital signal processor. The time is recovered in the digital code tracking loop, and final corrections are applied in the control processor. Other features of this design are: (1) drift-free digital mechanization; (2) high reliability of digital circuits; (3) flexible control capability of the microprocessor; and (4) potential for a high degree of digital VLSI chip development leading to compact, low-cost units.

Ould, P. C.

Minimal Power Latch for Single-Slope ADCs

Column-parallel analog-to-digital converters (ADCs) for imagers involve simultaneous operation of many ADCs. Single-slope ADCs are well adapted to this use because of their simplicity. Each ADC contains a comparator, comparing its input signal level to an increasing reference signal (ramp). When the ramp is equal to the input, the comparator triggers a latch that captures an encoded counter value (code). Knowing the captured code, the ramp value and hence the input signal are determined. In a column-parallel ADC, each column contains only the comparator and the latches; the ramp and code generation are shared. In conventional latch or flip-flop circuits, there is an input stage that tracks the input signal, and this stage consumes switching current every time the input changes. With many columns, many bits, and high code rates, this switching current can be substantial. It will also generate noise that may corrupt the analog signals. A latch was designed that does not track the input, and consumes power only at the instant of latching the data value. The circuit consists of two S-R (set-reset) latches, gated by the comparator. One is set by high data values and the other by low data values. The latches are cross-coupled so that the first one to set blocks the other. In order that the input data not need an inversion, which would consume power, the two latches are made in complementary polarity. This requires complementary gates from the comparator, instead of complementary data values, but the comparator only triggers once per conversion, and usually has complementary outputs to begin with. An efficient CMOS (complementary metal oxide semiconductor) implementation of this circuit is shown in the figure, where C is the comparator output, D is the data (code), and Q0 and Q1 are the outputs indicating the capture of a zero or one value. The latch for Q0 has a negative-true set signal and output, and is implemented using OR-AND-INVERT logic, while the latch for Q1 uses positive- true signals and is implemented using AND-OR-INVERT logic. In this implementation, both latches are cleared when the comparator is reset. Two redundant transistors are removed from the reset side of each latch, making for a compact layout. CMOS imagers with column-parallel ADCs have demonstrated high performance for remote sensing applications. With this latch circuit, the power consumption and noise can be further reduced. This innovation can be used in CMOS imagers and very-low-power electronics

Hancock, Bruce R.

Fiscal Year 2024 Software Quality Assurance Activities for the ARC Software

The continued goal of the ARC SQA project in the Advanced Reactor Technologies program of DOE is to resolve the QA gaps for the ARC software that limit, or prevent, commercialization of the software for industry users. This project started in earnest in fiscal year 2023 which saw the entire code system moved from a SVN repository to a GitLab repository and an associated software quality assurance plan (SQAP) developed and ratified. Most of the QA gaps in the ARC software were identified in collaboration with industry partners and work begin in fiscal year 2023 and continued in 2024. The primary documentation that is missing includes user manuals, user guides, software verification reports, and code coverage assessments. The SUMMAR manual was completed this fiscal year and work was started on creating manuals for SE2ANL, SE2RCT, and DASSH. Software verification work was carried out for DIF3D and REBUS in a previous program and the current fiscal year saw the completion of software verification reports for GAMSOR, GAMSRC, VARPOW, EvaluateFlux, and SUMMAR. The goal for the next fiscal year is to complete the PERSENT software verification work and begin planning the software verification work for DASSH, SE2ANL, and SE2RCT. The code coverage reports for DIF3D and MC2-3 were completed in the previous fiscal year and the goal is to generate code coverage reports for REBUS, GAMSOR, PERSENT, and DASSH in the coming fiscal year. A considerable amount of effort was spent in the current fiscal year working on the continuous integration capability for automated regression testing in GitLab. The first version of the testing was created in the previous fiscal year and applied to DIF3D and its utility programs. That testing was extended this year to cover GAMSOR, REBUS, and PERSENT. To accomplish this, the first version of the new testing methodology had to be updated to make a single output checking methodology viable for all of the ARC software. This will result in a single document to detail the automated regression testing methodology and minor documents to detail the tolerance settings that have been applied to the output for each ARC code. The previous methodology put into place with SVN would have required a separate document for each ARC code to detail the output checking methodology and the tolerance settings for the output from each code. Because some of our industry partners are providing funds to add new capabilities to the ARC software to meet their needs, all of which must be reviewed and approved by the SQA program funded by this project, a summary of that development work is detailed in this report. Overall progress on resolving the QA gaps has been good this year with the most impactful improvement for our industry partners in capability being the creation of a threaded version of DIF3D-VARIANT that allows the DIF3D, REBUS, and GAMSOR run times to be reduced by a factor of 4-6. The most impactful QA gap that was resolved was the software verification of GAMSRC and VARPOW.

97 MATHEMATICS AND COMPUTING

Calculation of two-dimensional inlet flow fields in a supersonic free stream: Program documentation and test cases

The use of a computer code for the calculation of two dimensional inlet flow fields in a supersonic free stream and a nonorthogonal mesh-generation code are illustrated by specific examples. Input, output, and program operation and use are given and explained for the case of supercritical inlet operation at a subdesign Mach number (M Mach free stream = 2.09) for an isentropic-compression, drooped-cowl inlet. Source listings of the computer codes are also provided.

Biringen, S. H.

Task 7: ADPAC User's Manual

The overall objective of this study was to develop a 3-D numerical analysis for compressor casing treatment flowfields. The current version of the computer code resulting from this study is referred to as ADPAC (Advanced Ducted Propfan Analysis Codes-Version 7). This report is intended to serve as a computer program user's manual for the ADPAC code developed under Tasks 6 and 7 of the NASA Contract. The ADPAC program is based on a flexible multiple- block grid discretization scheme permitting coupled 2-D/3-D mesh block solutions with application to a wide variety of geometries. Aerodynamic calculations are based on a four-stage Runge-Kutta time-marching finite volume solution technique with added numerical dissipation. Steady flow predictions are accelerated by a multigrid procedure. An iterative implicit algorithm is available for rapid time-dependent flow calculations, and an advanced two equation turbulence model is incorporated to predict complex turbulent flows. The consolidated code generated during this study is capable of executing in either a serial or parallel computing mode from a single source code. Numerous examples are given in the form of test cases to demonstrate the utility of this approach for predicting the aerodynamics of modem turbomachinery configurations.

Hall, E. J.

Automatic Synthesis of UML Designs from Requirements in an Iterative Process

The Unified Modeling Language (UML) is gaining wide popularity for the design of object-oriented systems. UML combines various object-oriented graphical design notations under one common framework. A major factor for the broad acceptance of UML is that it can be conveniently used in a highly iterative, Use Case (or scenario-based) process (although the process is not a part of UML). Here, the (pre-) requirements for the software are specified rather informally as Use Cases and a set of scenarios. A scenario can be seen as an individual trace of a software artifact. Besides first sketches of a class diagram to illustrate the static system breakdown, scenarios are a favorite way of communication with the customer, because scenarios describe concrete interactions between entities and are thus easy to understand. Scenarios with a high level of detail are often expressed as sequence diagrams. Later in the design and implementation stage (elaboration and implementation phases), a design of the system's behavior is often developed as a set of statecharts. From there (and the full-fledged class diagram), actual code development is started. Current commercial UML tools support this phase by providing code generators for class diagrams and statecharts. In practice, it can be observed that the transition from requirements to design to code is a highly iterative process. In this talk, a set of algorithms is presented which perform reasonable synthesis and transformations between different UML notations (sequence diagrams, Object Constraint Language (OCL) constraints, statecharts). More specifically, we will discuss the following transformations: Statechart synthesis, introduction of hierarchy, consistency of modifications, and "design-debugging".

Schumann, Johann

A Timer for Synchronous Digital Systems

The Real-Time Interferometer Control Systems Testbed (RICST) timing board is a VersaModule Eurocard (VME)-based board that can generate up to 16 simultaneous, phase-locked timing signals at a rate defined by the user. It can also generate all seven VME interrupt requests (IRQs). The RICST timing board is suitable mainly for robotic, aerospace, and real-time applications. Several circuit boards on the market are capable of generating periodic IRQs. Most are associated with Global Positioning System (GPS) receivers and Inter Range Instrumentation Group (IRIG) time-code generators, whereas this board uses either an internal VME clock or an externally generated clock signal to synchronize multiple components of the system. The primary advantage of this board is that there is no discernible jitter in the output clock waveforms because the signals are divided down from a high-frequency clock signal instead of being phase-locked from a lower frequency. The primary disadvantage to this board, relative to other periodic-IRQ-generating boards, is that it is more difficult to synchronize the system to wall clock time.

McKenney, Elizabeth

An Automatic Code Synthesizer

This paper describes the design and architecture fo an automatic code sysnthesizer we call the ACG. The input to the ACG is a list of facts that must hold for the generated code, along with domain-specific knowledge (design rules and patterns).

programming programming code programming productiv

Automatic finite element generators

The design and implementation of a software system for generating finite elements and related computations are described. Exact symbolic computational techniques are employed to derive strain-displacement matrices and element stiffness matrices. Methods for dealing with the excessive growth of symbolic expressions are discussed. Automatic FORTRAN code generation is described with emphasis on improving the efficiency of the resultant code.

Wang, P. S.