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DOE OSTI2025

Automating Testing of DUNE Electronics via a Finite State Machine

The Deep Underground Neutrino Experiment (DUNE) is a flagship international collaboration designed to study neutrinos tiny, nearly massless particles that may hold answers to fundamental questions about the Universe. Fermilab s Robotic Test Stand (RTS) plays a critical role in ensuring the quality of approximately 50,000 Application-Specific Integrated Circuit (ASIC) chips that will be used in DUNE s massive liquid argon detectors. These electronics will be inside the cryostat; therefore, they will need to have a high yield of working chips and low noise. To improve the automation and reliability of the RTS, this project focused on designing and implementing a Python-based finite state machine (FSM) to manage chip handling workflows. The FSM was developed as a modular software framework to coordinate robotic arm movements, manage chip tray positions, and monitor system states during testing. Key features include robust error handling routines, a pause/resume system for safe mid-cycle interruptions, and a simulation mode for iterative testing without hardware dependencies. The system was designed to prepare for seamless integration with RTS hardware components such as the robotic arm and vision system. This integration will streamline collaboration and enable efficient deployment of updates across the six total institutions performing testing. The outcomes of this internship contribute to Fermilab s mission to advance high-energy physics and support the DOE s national goals by directly improving the testing of equipment to be used in DUNE. The project also provided valuable experience in software design and contributing to the success of DUNE.

Kang, Caleb [William Rainey Harper Coll.]↗

DOE OSTI2025

Automating Testing of DUNE Electronics via a Finite State Machine

The Deep Underground Neutrino Experiment (DUNE) is a flagship international collaboration designed to study neutrinos—tiny, nearly massless particles that may hold answers to fundamental questions about the Universe. Fermilab’s Robotic Test Stand (RTS) plays a critical role in ensuring the quality of approximately 50,000 Application-Specific Integrated Circuit (ASIC) chips that will be used in DUNE’s massive liquid argon detectors. These electronics will be inside the cryostat; therefore, they will need to have a high yield of working chips and low noise. To improve the automation and reliability of the RTS, this project focused on designing and implementing a Python-based finite state machine (FSM) to manage chip handling workflows. The FSM was developed as a modular software framework to coordinate robotic arm movements, manage chip tray positions, and monitor system states during testing. Key features include robust error handling routines, a pause/resume system for safe mid-cycle interruptions, and a simulation mode for iterative testing without hardware dependencies. The system was designed to prepare for seamless integration with RTS hardware components such as the robotic arm and vision system. This integration will streamline collaboration and enable efficient deployment of updates across the six institutions performing testing. The outcomes of this internship contribute to Fermilab’s mission to advance high-energy physics and support the DOE’s national goals by directly improving the testing of equipment to be used in DUNE. The project also provided valuable experience in software design and contributing to the success of DUNE.

Kang, Caleb [Fermilab]↗

NASA NTRS1982

Test chips for custom ICs - Six kinds of test structures

Microelectronic test chips contain a number of test structures that are used for a variety of purposes in fabricating integrated circuits. For convenience, their use is divided into six groups: layout-rule evaluating, process-parameter extraction, device-parameter extraction, circuit-parameter extraction, initial-fabrication failure analysis, and reliability failure analysis. A given test structure can be used to gather information in a number of these groups. Examples are given here of the kinds of parameters that can be obtained in each of these groups. A table is included summarizing various device failures common to bulk CMOS and indicating failure mechanisms appearing after wafer fabrication and after stress.

Buehler, M. G.↗

NASA NTRS2011

Microcoil Spring Interconnects for Ceramic Grid Array Integrated Circuits

As integrated circuit miniaturization trends continue, they drive the need for smaller higher input/output (I/O) packages. Hermetically sealed ceramic area array parts are the package of choice by the space community for high reliability space flight electronic hardware. Unfortunately, the coefficient of thermal expansion mismatch between the ceramic area array package and the epoxy glass printed wiring board limits the life of the interconnecting solder joint. This work presents the results of an investigation by Marshall Space Flight Center into a method to increase the life of this second level interconnection by the use of compliant microcoil springs. The design of the spring and its attachment process are presented along with thermal cycling results of microcoil springs (MCS) compared with state-of-the-art ball and column interconnections. Vibration testing has been conducted on MCS and high lead column parts. Radio frequency simulation and measurements have been made and the MCS has been modeled and a stress analysis performed. Thermal cycling and vibration testing have shown MCS interconnects to be significantly more reliable than solder columns. Also, MCS interconnects are less prone to handling damage than solder columns. Future work that includes shock testing, incorporation into a digital signal processor board, and process evaluation of expansion from a 400 I/O device to a device with over 1,100 I/O is identified.

Strickland, S. M.↗

NASA NTRS2012

Distributed Motor Controller (DMC) for Operation in Extreme Environments

This paper presents an extreme environment capable Distributed Motor Controller (DMC) module suitable for operation with a distributed architecture of future spacecraft systems. This motor controller is designed to be a bus-based electronics module capable of operating a single Brushless DC motor in extreme space environments: temperature (-120 C to +85 C required, -180 C to +100 C stretch goal); radiation (>;20K required, >;100KRad stretch goal); >;360 cycles of operation. Achieving this objective will result in a scalable modular configuration for motor control with enhanced reliability that will greatly lower cost during the design, fabrication and ATLO phases of future missions. Within the heart of the DMC lies a pair of cold-capable Application Specific Integrated Circuits (ASICs) and a Field Programmable Gate Array (FPGA) that enable its miniaturization and operation in extreme environments. The ASICs are fabricated in the IBM 0.5 micron Silicon Germanium (SiGe) BiCMOS process and are comprised of Analog circuitry to provide telemetry information, sensor interface, and health and status of DMC. The FPGA contains logic to provide motor control, status monitoring and spacecraft interface. The testing and characterization of these ASICs have yielded excellent functionality in cold temperatures (-135 C). The DMC module has demonstrated successful operation of a motor at temperature.

SiGe↗

NASA NTRS1981

Impact of VLSI/VHSIC on satellite on-board signal processing

Forecasted improvements in IC fabrication techniques, such as the use of X-ray lithography, are expected to yield submicron circuit feature sizes within the decade of the 1980s. As dimensions decrease, reliability, cost, speed, power consumption and density improvements will be realized which have a significant impact on the capabilities of onboard spacecraft signal processing functions. This will in turn result in increases of the intelligence that may be deployed on spaceborne remote sensing platforms. Among programs oriented toward such goals are the silicon-based Very High Speed Integrated Circuit (VHSIC) researches sponsored by the U.S. Department of Defense, and efforts toward the development of GaAs devices which will compete with silicon VLSI technology for future applications. GaAs has an electron mobility which is five to six times that of silicon, and promises commensurate computation speed increases under low field conditions.

Aanstoos, J. V.↗

NASA NTRS1986

Multiple beam phased array for Space Station Control Zone Communications

The Space Station Communications Control Zone is a disk shaped region 40 nautical miles in diameter and 10 nautical miles thick centered about the Space Station. It is estimated that 6 simultaneous Multiple Access (MA) channels will be required to satisfy the projected communications needs within this zone. These channels will be used to communicate with MA users located anywhere within the Control Zone. This paper details the tradeoffs and design implementation of a multiple beam integrated phased array to provide antenna coverage of the Control Zone. The array is a compact, modular assembly using Gallium Arsenide circuits, microstrip elements, and advanced packaging techniques. This results in a small, reliable antenna system capable of meeting the projected Space Station requirements and flexible enough to grow and evolve as the Space Station communications needs develop.

Halsema, P. B.↗

NASA NTRS1980

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

Woo, D. S.↗

NASA NTRS2011

Miniaturized Airborne Imaging Central Server System

In recent years, some remote-sensing applications require advanced airborne multi-sensor systems to provide high performance reflective and emissive spectral imaging measurement rapidly over large areas. The key or unique problem of characteristics is associated with a black box back-end system that operates a suite of cutting-edge imaging sensors to collect simultaneously the high throughput reflective and emissive spectral imaging data with precision georeference. This back-end system needs to be portable, easy-to-use, and reliable with advanced onboard processing. The innovation of the black box backend is a miniaturized airborne imaging central server system (MAICSS). MAICSS integrates a complex embedded system of systems with dedicated power and signal electronic circuits inside to serve a suite of configurable cutting-edge electro- optical (EO), long-wave infrared (LWIR), and medium-wave infrared (MWIR) cameras, a hyperspectral imaging scanner, and a GPS and inertial measurement unit (IMU) for atmospheric and surface remote sensing. Its compatible sensor packages include NASA s 1,024 1,024 pixel LWIR quantum well infrared photodetector (QWIP) imager; a 60.5 megapixel BuckEye EO camera; and a fast (e.g. 200+ scanlines/s) and wide swath-width (e.g., 1,920+ pixels) CCD/InGaAs imager-based visible/near infrared reflectance (VNIR) and shortwave infrared (SWIR) imaging spectrometer. MAICSS records continuous precision georeferenced and time-tagged multisensor throughputs to mass storage devices at a high aggregate rate, typically 60 MB/s for its LWIR/EO payload. MAICSS is a complete stand-alone imaging server instrument with an easy-to-use software package for either autonomous data collection or interactive airborne operation. Advanced multisensor data acquisition and onboard processing software features have been implemented for MAICSS. With the onboard processing for real time image development, correction, histogram-equalization, compression, georeference, and data organization, fast aerial imaging applications, including the real time LWIR image mosaic for Google Earth, have been realized for NASA fs LWIR QWIP instrument. MAICSS is a significant improvement and miniaturization of current multisensor technologies. Structurally, it has a complete modular and solid-state design. Without rotating hard drives and other moving parts, it is operational at high altitudes and survivable in high-vibration environments. It is assembled from a suite of miniaturized, precision-machined, standardized, and stackable interchangeable embedded instrument modules. These stackable modules can be bolted together with the interconnection wires inside for the maximal simplicity and portability. Multiple modules are electronically interconnected as stacked. Alternatively, these dedicated modules can be flexibly distributed to fit the space constraints of a flying vehicle. As a flexibly configurable system, MAICSS can be tailored to interface a variety of multisensor packages. For example, with a 1,024x1,024 pixel LWIR and a 8,984x6,732 pixel EO payload, the complete MAICSS volume is approximately 7x9x11 in. (=18x23x28 cm), with a weight of 25 lb (=11.4 kg).

Sun, Xiuhong↗

NASA NTRSDate not supplied

High Temperature Devices for Aerospace Applications

This presentation will overview important new capabilities and benefits that next-generation higher temperature electronics promise for a variety of aerospace systems and missions. Initial aerospace infusions of higher temperature electronics to be discussed include jet engines and the prolonged robotic exploration of the Venus surface. Complete redesign of systems compared to prior conventional electronics practices would yield the most revolutionary benefits. However, the inherent higher risk and expense associated with new technology adoption will likely drive a more evolutionary technology infusion process, especially since flight qualification demands large safety margins and testing that ensures reliable operation for far longer than actual mission duration. SiC pn-junction based devices are inherently capable of the most durable operation at the highest application temperatures compared other transistor technologies, but such integrated circuits (ICs) will never achieve integration levels near today’s silicon ICs. Extreme temperature high-power devices will also be de-rated compared to room-temperature performance. While the high temperature market will always be small compared to the conventional temperature mass-market, compatibility and leveraging of existing foundry manufacturing is vital to the establishment of a sustainable high temperature electronics ecosystem sufficient to significantly improve aerospace systems.

High Temperature↗

DOE OSTI2024

SMART SiC Power ICs: Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (Final Technical Report)

This collaborative project was initiated with the goal of developing Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (SMART SiC Power ICs). In pursuit of this objective, innovative designs and fabrication processes were implemented, enabling the development of large-scale (>1 cm²) SiC Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits and high-voltage (400–600 V) lateral power MOSFETs (HV-LDMOS) on 150 mm 4H-SiC substrates. The resulting SMART SiC Power ICs are tailored to support a wide range of applications requiring diverse voltage and power levels, including automotive systems, industrial equipment, electronic data processing, energy harvesting, and power conditioning. To achieve the proposed ‘SMART’ technology for SiC ICs, the team focused on 1) the Development of highly scalable CMOS (with high channel mobilities for n-type and p-type MOSFETs), LDMOS (~600V, 10A rated), and IC technologies, 2) Establishment of a manufacturable process baseline in a production-grade-, 150mm, SiC fabrication facility, and 3) Demonstration of SMART SiC ICs. The project initially comprised of fabricating 5 lots. In lot 1 monolithic integration using a single process was achieved. Here, we were able to successfully accomplish Integrated HV NMOSFET with LV CMOS on N-epi/N+ Substrate. The HV NMOS demonstrated a Breakdown Voltage (BV) more than 600V. Circuit demonstration of CMOS was also another achievement from this lot. In lot 2, priority was in place for isolation and integration. Here we addressed the isolation concerns and integrated the HV NMOS and LV CMOS using the N-epi/P-epi/N+ substrate. Similar to the lot 1, we were able to achieve a BV of 600 V for HV NMOS. Optimized gate oxide process with high channel mobilities, better gate oxide reliability, development of SPICE models, successful ohmic process development, novel wafer area saving design layouts, P+ isolation schemes with channeling implantations and high temperature operational circuits demonstrations are some of the key highlights from lot 1 and lot2. In lot 3, discrete device performances of HV NMOS with a BV ~700V and reliable LV CMOS performances were achieved. Also, novel architectural solutions were successfully implemented to suppress the electric field crowding at the gate oxide for reliable operations. In lot 4, half bridge power driver ICs with a conversion efficiency of (target 90% to 95%) in the 1-5MHz switching frequency range for output power between 25 W to 3 kW have been included in. However, due to the unfortunate events of sudden foundry shutdown (SiCamore Semi) the processing of lot 4 wafers came to a complete stop (January 2024). Arrangements have recently been made to shift the fabrication to another foundry, General Electric Aerospace. The fabrication process now on course (as of December 2024). Characterizations are delayed due to this unfortunate circumstance. The proposed trench architectural-based devices and ICs (lot 5) underwent modifications from the original project proposal. This change was necessitated by limitations in the availability of trench-based processes at commercial production-grade fabrication facilities in the US. Apart from above achievements, a Process Development Kit (PDK) was successfully developed for planar type SiC CMOS/LDMOS.

42 ENGINEERING↗

NASA NTRS2017

High Density Packaging Technologies for RF Electronics in Small Spacecraft

This paper will describe a few high density packaging technologies which we are currently exploring for use in current and future small spacecraft applications. The three categories of technologies include organic multichip modules (MCMs), ceramic leadless surface mount technology (SMT) and 3D printed waveguide structures. There are many other packaging technologies that currently exist but these three were selected in part due to their long heritage in various commercial, military and space applications along with each having a relatively clear path to flight. For each of these technologies, detailed examples will be included in which hardware has been fabricated and tested for use in RF electronics for spacecraft transponders. The organic MCM example will be described in most detail and it utilizes a packaging technology by the name of CoreEZ which is a trademark of i3 Electronics. This MCM has shrunk a portion of our electronics down to 1/8th of its previous area. The CoreEZ technology has been shown to be rad hard beyond a total ionizing dose (TID) of 300kRad and the MCM which was fabricated has gone through thermal cycling and shown to have no degradation in performance. The ceramic leadless package examples include packages from high reliability manufactures by the name of KCB solutions and Barry Industries. In the case of KCB solutions, we have multiple products that will be described including a hermetic ceramic carrier which houses three microwave monolithic integrated circuits (MMICs) along with small discrete components. Finally, we will discuss the results of our search for a 3D printing process that allows us to reduce the cost and volume of our waveguide filters and diplexers for low cost small satellite applications. We have fabricated a few prototypes using direct metal laser sintering (DMLS) and metal coated plastics. Each of these packaging technology discussions will have a brief overview of its current and future use.

Aquirre, Fernando↗

NASA NTRS2016

High Density Packaging Technologies for RF Electronics in Small Spacecraft

Schatzel, Donald↗

DOE OSTI2025

PID-Regulated Heating System for PIP-II Reference Line

The Proton Improvement Project-2 centers on building a new superconducting linear particle accelerator (Linac) at Fermilab. At the heart of the accelerator is the reference line, a critical system that defines the ideal path for the particle beam as it passes through magnets, RF cavities, and other beamline elements. Temperature stability is crucial for the reliable operation of RF components, such as mixers and filters. Fluctuations affect key performance parameters like conversion loss, isolation, and linearity. To mitigate any drift caused by ambient temperature changes, a heating plate assembly is utilized to maintain key components at a controlled temperature of 40°C. The system utilizes an aluminum 36”x36”x0.5” heat plate powered by a MOSFET-based control circuit, delivering approximately 460 W of thermal energy through a resistor array. Real-time temperature feedback is provided by a PT100 Resistance Temperature Detector (RTD), which interfaces with a Proportional–Integral–Derivative (PID) control algorithm to maintain closed-loop temperature regulation. The control signal actively modulates the gate voltage of an N channel MOSFET, dynamically adjusting power delivery in response to deviations from the temperature setpoint. Simulations and LTspice models validate the functionality and responsiveness of the circuit under varying conditions. The prototype has successfully demonstrated stable thermal control, paving the way for integration into the PIP-II infrastructure. The final design will feature an expanded resistor array, as well as communication with a PLC for continuous data acquisition and diagnostics. This work directly supports Fermilab’s broader mission by contributing to the stability and reliability of core accelerator systems, enhancing the precision of particle beam delivery for future physics experiments.

Mosher, Alexander [Fermilab]↗

NASA NTRS1980

Optimizing costs of VLSI circuits

Report analyzes costs of developing and producing low-production-volume, customized VLSI (very large-scale, integrated) circuits. Relationship is developed between IC cost and electronic system cost using IC cost models based on design/fabrication approach. Emphasis is on development of understanding between cost and volume for custom circuits to be used by NASA. Reliability is major cost component in models. Report is divided into five sections and includes four appendices with useful reference literature.

Cook, K. B., Jr.↗

NASA NTRS2017

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

Today's launch vehicles complex electronic and avionics systems heavily utilize Field Programmable Gate Array (FPGA) integrated circuits (IC) for their superb speed and reconfiguration capabilities. Consequently, FPGAs are prevalent ICs in communication protocols such as MILSTD- 1553B and in control signal commands such as in solenoid valve actuations. This paper will identify reliability concerns and high level guidelines to estimate FPGA total failure rates in a launch vehicle application. The paper will discuss hardware, hardware description language, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC. The hardware description language portion will discuss the high level FPGA programming languages and software/code reliability growth. The radiation portion will discuss FPGA susceptibility to space environment radiation.

Al Hassan, Mohammad↗

NASA NTRS1984

Definition, analysis and development of an optical data distribution network for integrated avionics and control systems. Part 2: Component development and system integration

Fiber optic transmission is emerging as an attractive concept in data distribution onboard civil aircraft. Development of an Optical Data Distribution Network for Integrated Avionics and Control Systems for commercial aircraft will provide a data distribution network that gives freedom from EMI-RFI and ground loop problems, eliminates crosstalk and short circuits, provides protection and immunity from lightning induced transients and give a large bandwidth data transmission capability. In addition there is a potential for significantly reducing the weight and increasing the reliability over conventional data distribution networks. Wavelength Division Multiplexing (WDM) is a candidate method for data communication between the various avionic subsystems. With WDM all systems could conceptually communicate with each other without time sharing and requiring complicated coding schemes for each computer and subsystem to recognize a message. However, the state of the art of optical technology limits the application of fiber optics in advanced integrated avionics and control systems. Therefore, it is necessary to address the architecture for a fiber optics data distribution system for integrated avionics and control systems as well as develop prototype components and systems.

Yen, H. W.↗

NASA NTRS1997

Logic Design Pathology and Space Flight Electronics

Logic design errors have been observed in space flight missions and the final stages of ground test. The technologies used by designers and their design/analysis methodologies will be analyzed. This will give insight to the root causes of the failures. These technologies include discrete integrated circuit based systems, systems based on field and mask programmable logic, and the use computer aided engineering (CAE) systems. State-of-the-art (SOTA) design tools and methodologies will be analyzed with respect to high-reliability spacecraft design and potential pitfalls are discussed. Case studies of faults from large expensive programs to "smaller, faster, cheaper" missions will be used to explore the fundamental reasons for logic design problems.

Katz, Richard↗