Development of ion implantation techniques for microelectronics
Ion implantation process for fabricating active devices in high bandgap semiconductor materials for high temperature operation
Dunlap, H. L.↗
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The millimeter wave super-Schottky diode detector
The 31 and 92 GHz measurements of the superconductor-Schottky diode extended to millimeter wavelengths by a redesign of the semiconductor interface are reported. Diodes were fabricated by pulse electroplating Pb on 2 x 10 to the 19th/cu cm p-Ga-As etched with HCl; a thin Au overplate is deposited to protect the Pb film from degradation and to improve its lifetime. The noise performance was almost ideal at 31 and 92 GHz; it was concluded that this diode is a quantum-limited-detector at 31 GHz, with excessive parasitic losses at 92 GHz.
Silver, A. H.↗
Proceedings of the Conference on High-temperature Electronics
The development of electronic devices for use in high temperature environments is addressed. The instrumentational needs of planetary exploration, fossil and nuclear power reactors, turbine engine monitoring, and well logging are defined. Emphasis is place on the fabrication and performance of materials and semiconductor devices, circuits and systems and packaging.
Source record↗
Study of Contact Resistances in Integrated Circuits
Techniques explored in search for rapid, reliable test. Resistances of aluminum/silicon contacts and methods to measure subjects of NASA report. Study with three tasks undertaken to evaluate nature and reliability of large numbers of semiconductor contacts of type now being fabricated in integrated circuits: Develop yield analysis for series strings of contacts using wafer-level electrical measurements, and identify different types of faults by visual inspection; develop wafer-level tests to evaluate reliability of contact strings; and develop mathematical model for current flow in contacts and examine contact region for evidence of micro-alloying.
Buehler, M. G.↗
Fluidized-Bed Cleaning of Silicon Particles
Fluidized-bed chemical cleaning process developed to remove metallic impurities from small silicon particles. Particles (250 micrometer in size) utilized as seed material in silane pyrolysis process for production of 1-mm-size silicon. Product silicon (1 mm in size) used as raw material for fabrication of solar cells and other semiconductor devices. Principal cleaning step is wash in mixture of hydrochloric and nitric acids, leaching out metals and carrying them away as soluble chlorides. Particles fluidized by cleaning solution to assure good mixing and uniform wetting.
Rohatgi, Naresh K.↗
Heavy-ion induced single-event upset in integrated circuits
The cosmic ray environment in space can affect the operation of Integrated Circuit (IC) devices via the phenomenon of Single Event Upset (SEU). In particular, heavy ions passing through an IC can induce sufficient integrated current (charge) to alter the state of a bistable circuit, for example a memory cell. The SEU effect is studied in great detail in both static and dynamic memory devices, as well as microprocessors fabricated from bipolar, Complementary Metal Oxide Semiconductor (CMOS) and N channel Metal Oxide Semiconductor (NMOS) technologies. Each device/process reflects its individual characteristics (minimum scale geometry/process parameters) via a unique response to the direct ionization of electron hole pairs by heavy ion tracks. A summary of these analytical and experimental SEU investigations is presented.
Zoutendyk, J. A.↗
Further study of inversion layer MIS solar cells
Many inversion layer metal-insulator-semiconductor (IL/MIS) solar cells have been fabricated. As of today, the best cell fabricated by us has a 9.138 percent AMO efficiency, with FF = 0.641, V(sub OC) = 0.557 V, and I(sub SC) = 26.9 micro A. Efforts made for fabricating an IL/MOS solar cell with reasonable efficiencies are reported. The more accurate control of the thickness of the thin layer of oxide between aluminum and silicon of the MIS contacts has been achieved by using two different process methods. Comparison of these two different thin oxide processings is reported. The effects of annealing time of the sample are discussed. The range of the resistivity of the substrates used in the IL cell fabrication is experimentally estimated. Theoretical study of the MIS contacts under dark conditions is addressed.
Ho, Fat Duen↗
Competitive neural architecture for hardware solution to the assignment problem
The architecture for competitive assignment is described with attention given to the VLSI design and critical circuits fabricated in complementary metal-oxide semiconductor. The local application of association costs to processing units reduces the connectivity to the number of VLSI-compatible processing units. 'Hysteretic annealing' is discussed and when compared to mean-field annealing is found to enhance processing-unit gain and provide near-optimal solutions in about 150 microsec.
Eberhardt, S. P.↗
Evaluation of light emitting diode characteristics for a space-based plant irradiation source
Light emitting diodes (LEDs) are a promising irradiation source for plant growth in space. Improved semiconductor technology has yielded LED devices fabricated with gallium aluminum arsenide (GaAlAs) chips which have a high efficiency for converting electrical energy to photosynthetically active radiation. Specific GaAlAs LEDs are available that emit radiation with a peak wavelength near the spectral peak of maximum quantum action for photosynthesis. The electrical conversion efficiency of installed systems (μmol s -1 of photosynthetic photons per watt) of high output LEDs can be within 10% of that for high pressure sodium lamps. Output of individual LEDs were found to vary by as much as 55 % from the average of the lot. LED ratings, in mcd (luminous intensity per solid angle), were found to be proportional to total photon output only for devices with the same dispersion angle and spectral peak. Increasing current through the LED increased output but also increased temperature with a consequent decrease in electrical conversion efficiency. A photosynthetic photon flux as high as 900 μmol m -2 s -1 has been produced on surfaces using arrays with LEDs mounted 7.6 mm apart, operating at a current of 50 mA device -1 and at an installed density of approximately 17,200 lamps m -2 of irradiated area. Advantages of LEDs over other electric light sources for use in space systems include long life, minimal mass and volume and being a solid state device.
D J Barta↗
Endotaxial growth of CoSi2 within (111) oriented Si in a molecular beam epitaxy system
A new mode of growth is reported in which buried metallic layers can be fabricated within a single-crystal semiconductor through preferential subsurface growth on previously-grown 'seed' regions. The deposition of Co at 800 C at a rate of 0.01 nm/s on (111) Si substrates containing buried CoSi2 columns 40-100 nm below the Si surface results in the growth and coalescence of these subsurface columns. The formation of a CoSi2 layer on the Si surface is suppressed by this growth mode. It is proposed that the high diffusion rate of Co at 800 C, coupled with the high growth rate of CoSi2 at the subsurface columns, is responsible for this preferred 'endotaxial' growth mode. This growth technique was used to produce a continuous buried single-crystal layer of CoSi2 under a single-crystal Si capping layer.
George, T.↗
Metal-Film Hall-Effect Devices
Large positive and negative Hall coefficients achievable. Family of Hall-effect devices made from multilayer metal films instead of semiconductor materials. Metal films easier to fabricate; formed by deposition on variety of substrates, and leads readily attached to them. Fabricated with larger areas, potentially more reliable, and less affected by impurities. Also used to measure magnetic fields. Devices especially useful at low temperatures.
Peters, Palmer N.↗
Studies of Large-Area Inversion-Layer Metal-Insulator-Semiconductor (IL/MIS) Solar Cells and Arrays
Many inversion-layer metal-insulator-semiconductor (IL/MIS) solar cells have been fabricated. There are around eighteen 1 cm(exp 2) IL/MIS solar cells which have efficiencies greater than 7%. There are only about three 19 cm(exp 2) IL/MIS cells which have efficiencies greater than 4%. The more accurate control of the thickness of the thin layer of oxide between aluminum and silicon of the MIS contacts has been achieved. A lot of effort and progress have been made in this area. A comprehensive model for MIS contacts under dark conditions has been developed that covers a wide range of parameters. It has been applied to MIS solar cells. One of the main advantages of these models is the prediction of the range of the thin oxide thickness versus the maximum efficiencies of the MIS solar cells. This is particularly important when the thickness is increased to 25 A. This study is very useful for our investigation of the IL/MIS solar cells. The two-dimensional numerical model for the IL/MIS solar cells has been tried to develop and the results are presented in this report.
Ho, Fat Duen↗
Plasma Deposited SiO2 for Planar Self-Aligned Gate Metal-Insulator-Semiconductor Field Effect Transistors on Semi-Insulating InP
Metal-insulator-semiconductor (MIS) field effect transistors were fabricated on InP substrates using a planar self-aligned gate process. A 700-1000 A gate insulator of Si02 doped with phosphorus was deposited by a direct plasma enhanced chemical vapor deposition at 400 mTorr, 275 C, 5 W, and power density of 8.5 MW/sq cm. High frequency capacitance-voltage measurements were taken on MIS capacitors which have been subjected to a 700 C anneal and an interface state density of lxl0(exp 11)/eV/cq cm was found. Current-voltage measurements of the capacitors show a breakdown voltage of 107 V/cm and a insulator resistivity of 10(exp 14) omega cm. Transistors were fabricated on semi-insulating InP using a standard planar self-aligned gate process in which the gate insulator was subjected to an ion implantation activation anneal of 700 C. MIS field effect transistors gave a maximum extrinsic transconductance of 23 mS/mm for a gate length of 3 microns. The drain current drift saturated at 87.5% of the initial current, while reaching to within 1% of the saturated value after only 1x10(exp 3). This is the first reported viable planar InP self-aligned gate transistor process reported to date.
Tabory, Charles N.↗
600 C Logic Gates Using Silicon Carbide JFET's
Complex electronics and sensors are increasingly being relied on to enhance the capabilities and efficiency of modernjet aircraft. Some of these electronics and sensors monitor and control vital engine components and aerosurfaces that operate at high temperatures above 300 C. However, since today's silicon-based electronics technology cannot function at such high temperatures, these electronics must reside in environmentally controlled areas. This necessitates either the use of long wire runs between sheltered electronics and hot-area sensors and controls, or the fuel cooling of electronics and sensors located in high-temperature areas. Both of these low-temperature-electronics approaches suffer from serious drawbacks in terms of increased weight, decreased fuel efficiency, and reduction of aircraft reliability. A family of high-temperature electronics and sensors that could function in hot areas would enable substantial aircraft performance gains. Especially since, in the future, some turbine-engine electronics may need to function at temperatures as high as 600 C. This paper reports the fabrication and demonstration of the first semiconductor digital logic gates ever to function at 600 C. Key obstacles blocking the realization of useful 600 C turbine engine integrated sensor and control electronics are outlined.
Neudeck, Philip G.↗
Stable Electrical Operation of 6H-SiC JFETs and ICs for Thousands of Hours at 500 C
The fabrication and testing of the first semiconductor transistors and small-scale integrated circuits (ICs) to achieve up to 3000 h of stable electrical operation at 500 C in air ambient is reported. These devices are based on an epitaxial 6H-SiC junction field-effect transistor process that successfully integrated high temperature ohmic contacts, dielectric passivation, and ceramic packaging. Important device and circuit parameters exhibited less than 10% of change over the course of the 500 C operational testing. These results establish a new technology foundation for realizing durable 500 C ICs for combustion-engine sensing and control, deep-well drilling, and other harsh-environment applications.
Neudeck, Philip G.↗
Growth Mechanism of Nanowires: Ternary Chalcogenides
In the past two decades there has been a large rise in the investment and expectations for nanotechnology use. Almost every area of research has projected improvements in sensors, or even a promise for the emergence of some novel device technologies. For these applications major focuses of research are in the areas of nanoparticles and graphene. Although there are some near term applications with nanowires in photodetectors and other low light detectors, there are few papers on the growth mechanism and fabrication of nanowire-based devices. Semiconductor nanowires exhibit very favorable and promising optical properties, including high transparency and a several order of magnitude better photocurrent than thin film and bulk materials. We present here an overview of the mechanism of nanowire growth from the melt, and some preliminary results for the thallium arsenic selenide material system. Thallium arsenic selenide (TAS) is a multifunctional material combining excellent acousto-optical, nonlinear and radiation detection properties. We observed that small units of (TAS) nanocubes arrange and rearrange at moderate melt undercooling to form the building block of a nanowire. In some cases very long wires (less than mm) are formed. Since we avoided the catalyst, we observed self-nucleation and uncontrolled growth of wires from different places.
Singh, N. B.↗
Assessment of Cryogenic Analog Electronics for Lunar Environment
Assessment of Analog Electronics for Lunar Power Hibernation Non-nuclear robotic spacecraft on the Moon may not reliably operate past the first lunar day due to the subsequent long lunar night with an extreme low temperature range of 50K-100K. To address this concern, the NASA Glenn Research Center is developing a lunar power hibernation protocol that could enable spacecraft to passively survive the lunar night without any additional heating source and then reactivate at lunar dawn. Low cost lunar robotic missions could extend their mission lifetime from a single lunar cycle to potentially many months, thus greatly extending science data gathering and return on investment for commercial missions. This approach centers on evidence that lithium-ion battery cells can recover to full operation after being subjected to cryogenic temperatures. Exploiting this battery capability requires that all spacecraft electronics, including power system and avionics, passively tolerate the extreme cold without degradation. Key elements in the power system will also need to be capable of actively operating in the extreme cold to perform the functions required to restore the system to full operation after solar power returns at lunar dawn. This presentation provides an assessment of extreme-cold tolerance and operational capability of analog electronics where choices in semiconductor material, device type, and circuit fabrication technology has a dramatic impact on circuit behavior and reliability at low temperatures.
Lunar↗
Future Development of Dense Ferroelectric Memories for Space Applications
The availability of high density, radiation tolerant, nonvolatile memories is critical for space applications. Ferroelectric memories, when fabricated with radiation hardened complementary metal oxide semiconductors (CMOS), can be manufactured and packaged to provide high density replacements for Flash memory, which is not radiation tolerant. Previous work showed ferroelectric memory cells to be resistant to single event upsets and proton irradiation, and ferroelectric storage capacitors to be resistant to neutron exposure. In addition to radiation hardness, the fast programming times, virtually unlimited endurance, and low voltage, low power operation make ferroelectric memories ideal for space missions. Previously, a commercial double level metal 64-kilobit ferroelectric memory was presented. Although the capabilities of radiation hardened wafer fabrication facilities lag behind those of the most modern commercial wafer fabrication facilities, several paths to achieving radiation tolerant, dense ferroelectric memories are emerging. Both short and long term solutions are presented in this paper. Although worldwide major semiconductor companies are introducing commercial ferroelectric memories, funding limitations must be overcome to proceed with the development of high density, radiation tolerant ferroelectric memories.
Philpy, Stephen C.↗