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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records

Performance Evaluation of a Two-Dimensional Flood Model on Heterogeneous High-Performance Computing Architectures

This paper describes the implementation of a two-dimensional hydrodynamic flood model with two different numerical schemes on heterogeneous high-performance computing architectures. Both schemes were able to solve the nonlinear hyperbolic shallow water equations using an explicit upwind first-order approach on finite differences and finite volumes, respectively, and were conducted using MPI and CUDA. Four different test cases were simulated on the Summit supercomputer at Oak Ridge National Laboratory. Both numerical schemes scaled up to 128 nodes (768 GPUs) with a maximum 98.2x speedup of over 1 GPU. The lowest run time for the 10 day Hurricane Harvey event simulation at 5 meter resolution (272 million grid cells) was 50 minutes. GPUDirect communication proved to be more convenient than the standard communication strategy. Both strong and weak scaling are shown.

Sharif, Md Bulbul↗

The Computing Architectures Donnybrook

Explains the context and framework I'm creating as the Computer Architectures associate editor for IEEE Computer Magazine. The article is largely a historical recitation of computer architectures.

Williams, Joseph A.↗

Emerging Computing Architectures: Simulation of Power Electronics in Power Grids

As the penetration of power electronics increases in power grids, new computing architectures needed to be evaluated for the simulation of high-fidelity models of power electronics in power grids in operations. In this paper, emerging computing architectures such as quantum processing units are evaluated for the simulation of power electronics in power grids. A hybrid algorithm based on classical computing and quantum computing is developed and tested for different use cases of electromagnetic transient (EMT) simulation of power electronics (PE)-based systems and simple circuits. The algorithms needed to simulate power electronics in emerging computing architectures are discussed and thereafter, simulation results are shown.

Debnath, Suman↗

Charaterization of Emerging Computing Architectures for Dynamic Simulation of Future Power Grids with Large-Scale Power Electronics

The increasing penetration of power electronics in power grids significantly raises the computing requirements in a real-time (and/or fast) simulation of the power grid. The real-time simulation is an enabler for evaluating controllers, protection systems, new equipment, and twinning. In this paper, emerging computing architectures such as tensor processing units (TPU), neural/neuromorphic processing units (NPU), and quantum processing units (QPU) are introduced and characterized for the real-time (and/or fast) simulation of power electronics-dominated power grids. The metrics and the process to characterize emerging computing architectures to perform real-time (and/or fast) simulations of future power grids with power electronics are discussed. Three of the emerging computing units are characterized based on these metrics and the process developed. This characterization will enable identification and comparison of emerging computing architectures that can perform real-time (and/or fast) simulation of future power grids.

Choi, Jongchan↗

Energy Use in Quantum Data Centers: Scaling the Impact of Computer Architecture, Qubit Performance, Size, and Thermal Parameters

As quantum computers increase in size, the total energy used by a quantum data center, including the cooling, will become a greater concern. The cooling requirements of quantum computers, which operate at temperatures near absolute zero, are determined by computing system parameters, including the number and type of physical qubits, the packaging efficiency of the system, and the split between circuits operating at cryogenic temperatures and those operating at room temperature. When combined with thermal system parameters such as cooling efficiency and cryostat heat transfer, the total energy use can be determined using a first-principles energy model. These models show that cooling of quantum computers differs in two fundamental ways from conventional data centers: (1) the energy required for cooling is much greater than the energy required for computation, and (2) the cooling loads are sensitive to the computational architecture. The temperature requirements for different qubit types can change energy requirements by orders of magnitude. Power use and computational power, as quantified by quantum volume, are analytically correlated. Approaches are identified for minimizing energy use in integrated quantum systems relative to computational power. Furthermore, designing a sustainable quantum computer will require both efficient cooling and system design that minimizes cooling requirements.

97 MATHEMATICS AND COMPUTING↗

Software for Sparse Tensor Decomposition on Emerging Computing Architectures

In this paper, we develop software for decomposing sparse tensors that is portable to and performant on a variety of multicore, manycore, and GPU computing architectures. The result is a single code whose performance matches optimized architecture-specific implementations. The key to a portable approach is to determine multiple levels of parallelism that can be mapped in different ways to different architectures, and we explain how to do this for the matricized tensor times Khatri--Rao product (MTTKRP), which is the key kernel in canonical polyadic tensor decomposition. Our implementation leverages the Kokkos framework, which enables a single code to achieve high performance across multiple architectures that differ in how they approach fine-grained parallelism. We also introduce a new construct for portable thread-local arrays, which we call compile-time polymorphic arrays. Not only are the specifics of our approaches and implementation interesting for tuning tensor computations, but they also provide a roadmap for developing other portable high-performance codes. As a last step in optimizing performance, we modify the MTTKRP algorithm itself to do a permuted traversal of tensor nonzeros to reduce atomic-write contention. Lastly, we test the performance of our implementation on 16- and 68-core Intel CPUs and the K80 and P100 NVIDIA GPUs, showing that we are competitive with state-of-the-art architecture-specific codes while having the advantage of being able to run on a variety of architectures.

97 MATHEMATICS AND COMPUTING↗

Building a quantum computing architecture using 3D superconducting cavities

Quantum computers promise advantages over classical machines for solving certain complex problems, but building processors that truly deliver this advantage remains a central challenge, particularly due to limited coherence times. Three-dimensional superconducting radio-frequency (SRF) cavities offer an attractive platform due to their exceptionally long lifetimes. However, since these harmonic systems require nonlinear elements, such as transmons, for control, additional losses are often introduced. In this talk, I will present a multimode quantum system based on an elliptical SRF cavity hosting two cavity modes weakly coupled to an ancillary transmon circuit. This architecture is carefully engineered to preserve coherence while enabling efficient control. By optimizing the design to mitigate transmon-induced decoherence, we realize single-photon lifetimes of 20.6 ms and 15.6 ms in the two modes, with pure dephasing times exceeding 40 ms. Using sideband interactions and error-resilient protocols, such as measurement-based correction and post-selection, we demonstrate high-fidelity state control, including preparation of Fock states up to N=20 with fidelities above 95% (to our knowledge, the highest reported to date), as well as high-fidelity two-mode entanglement. These results highlight 3D SRF cavities as a robust foundation for qudit-based quantum information processing, harnessing the large Hilbert space of cavity modes. I will conclude by outlining strategies to further enhance coherence in both cavities and ancilla qubits, and discuss pathways toward scaling this architecture into a larger quantum computing platform.

Roy, Tanay [Fermilab]↗

Performance Optimization of a Beam Dynamics PIC Code On Hybrid Computer Architectures

The self-consistent multi-particle tracking based on particle-in-cell method (PIC) has been widely used in particle accelerator beam dynamics study. However, the PIC simulation is time-consuming and needs to use modern parallel computers for high resolution applications. In this paper, we implemented and optimized a parallel beam dynamics PIC code on two types of hybrid parallel computer architectures: one is the GPU and GPU cluster, while the other is the "Knight Landing" CPU cluster.

Liu, Zhicong↗

Porting hypre to heterogeneous computer architectures: Strategies and experiences

We report that linear systems are occurring in many applications, and solving them can take a large amount of the total simulation time. The high performance library hypre provides a variety of interfaces and linear solvers, including various multigrid methods, that have achieved good scalability on a variety of homogeneous parallel computer architectures. Heterogeneous architectures with nodes that have both CPUs and accelerators provide new challenges, since they require more fine-grained parallelism and reduced data movement between different memories on a single node as well as across nodes. We will discuss our experiences and strategies to port hypre to heterogeneous computers with accelerators, including the design of a new memory model, the use of abstractions, the BoxLoop macros in the structured and semi-structured interfaces, and the restructuring of algebraic multigrid (AMG) into modular components. We present numerical experiments comparing CPU and GPU performance for several test problems.

97 MATHEMATICS AND COMPUTING↗

Analysis of Vector Particle-In-Cell (VPIC) memory usage optimizations on cutting-edge computer architectures

Vector Particle-In-Cell (VPIC) is one of the fastest plasma simulation codes in the world, with particle numbers ranging from one trillion on the first petascale system, Roadrunner, to ten trillion particles on the more recent Blue Waters supercomputer. As supercomputers continue to grow rapidly in size, so too does the gap between computing capability and memory capability. Current memory systems limit VPIC simulations greatly as the maximum number of particles that can be simulated directly depends on the available memory. In this study, we present a suite of VPIC memory optimizations (i.e., particle weight, half-precision, and fixed-point optimizations) that enable a significant increase in the number of particles in VPIC simulations. Here, we assess the optimizations’ impact on memory and runtime performance for a suite of cutting-edge computer architectures such has the NVIDIA V100 GPU, the IBM Power9, and the Fujitsu A64FX architectures. Our optimizations enable a 31.25% reduction in memory usage and up to 40% increase in the number of particles. This paper extends our work on developing particle storage format optimizations Tan et al.

97 MATHEMATICS AND COMPUTING↗

aphBO-2GP-3B: a budgeted asynchronous parallel multi-acquisition functions for constrained Bayesian optimization on high-performing computing architecture

High-fidelity complex engineering simulations are often predictive, but also computationally expensive and often require substantial computational efforts. The mitigation of computational burden is usually enabled through parallelism in high-performance cluster (HPC) architecture. Optimization problems associated with these applications is a challenging problem due to the high computational cost of the high-fidelity simulations. In this paper, an asynchronous parallel constrained Bayesian optimization method is proposed to efficiently solve the computationally expensive simulation-based optimization problems on the HPC platform, with a budgeted computational resource, where the maximum number of simulations is a constant. The advantage of this method are three-fold. Firstly, the efficiency of the Bayesian optimization is improved, where multiple input locations are evaluated parallel in an asynchronous manner to accelerate the optimization convergence with respect to physical runtime. This efficiency feature is further improved so that when each of the inputs is finished, another input is queried without waiting for the whole batch to complete. Second, the proposed method can handle both known and unknown constraints. Third, the proposed method samples several acquisition functions based on their rewards using a modified GP-Hedge scheme. The proposed framework is termed aphBO-2GP-3B, which means asynchronous parallel hedge Bayesian optimization with two Gaussian processes and three batches. The numerical performance of the proposed framework aphBO-2GP-3B is comprehensively benchmarked using 16 numerical examples, compared against other 6 parallel Bayesian optimization variants and 1 parallel Monte Carlo as a baseline, and demonstrated using two real-world high-fidelity expensive industrial applications. The first engineering application is based on finite element analysis (FEA) and the second one is based on computational fluid dynamics (CFD) simulations.

97 MATHEMATICS AND COMPUTING↗

Domain-specific virtual processors as a portable programming and execution model for parallel computational workloads on modern heterogeneous high-performance computing architectures

We advocate domain-specific virtual processors (DSVP) as a portability layer for expressing and executing domain-specific computational workloads on modern heterogeneous HPC architectures, with applications in quantum chemistry. Specifically, in this article we extend, generalize and better formalize the concept of a domain-specific virtual processor as applied to scientific high-performance computing. In particular, we introduce a system-wide recursive (hierarchical) hardware encapsulation mechanism into the DSVP architecture and specify a concrete microarchitectural design of an abstract DSVP from which specialized DSVP implementations can be derived for specific scientific domains. Furthermore, we demonstrate, an example of a domain-specific virtual processor specialized to numerical tensor algebra workloads, which is implemented in the ExaTENSOR library developed by the author with a primary focus on the quantum many-body computational workloads on large-scale GPU-accelerated HPC platforms.

97 MATHEMATICS AND COMPUTING↗

High-Order Preconditioners for Modern Computing Architectures: Line-Based Discontinuous Galerkin Method on GPUs

The goals of our project are to be able to overcome issues that plague computing in modern architecture such as limited memory bandwidth, badly conditioned Jacobians, and restrictive time steps. We begin by describing the line-based discontinuous Galerkin (line DG) method for a scalar two-dimensional problem. Line DG has been shown to provide a significant increase in sparsity for Jacobian matrix, especially in the diagonal block elements. In addition to this, the implicit time integration scheme helps alleviate the time step restriction but requires solving a (potentially badly conditioned) linear system. We can precondition the linear system to facilitate the solution. Since we want to solve the system on the GPU, the increase in sparsity from the line DG method is helpful to alleviate the memory issue. We successfully implemented a computation of the Jacobian on the CPU and are currently working on the GPU implementation. Finally, I discuss how this opportunity to intern at Lawrence Livermore National Laboratory through the National Science Foundation Mathematical Sciences Graduate Internship has affected my personal and professional growth.

97 MATHEMATICS AND COMPUTING↗

Neuromorphic computing architecture with dynamically accessible contexts

Various technologies pertaining to allocating computing resources of a neuromorphic computing system are described herein. Subgraphs of a neural algorithm graph to be executed by the neuromorphic computing system are identified. The subgraphs are each executed by a group of neuron circuits serially. Output data generated by execution of the subgraphs are provided to the same or a second group of neuron circuits at a same time or with associated timing data indicative of a time at which the output data was generated. The same or second group of neuron circuits performs one or more processing operations based upon the output data.

Aimone, James Bradley↗

An ATLAS distributed computing architecture for HL-LHC

The ATLAS collaboration started a process to understand the computing needs for the High Luminosity LHC era. Based on our best understanding of the computing model input parameters for the HL-LHC data taking conditions, results indicate the need for a larger amount of computational and storage resources with respect to the projection of constant yearly budget for computing in 2026. Filling the gap between the projection and the needs will be one of the challenges in preparation for HL-LHC. While the gains from improvements in offline software will play a crucial role in this process, a different model for data processing, management, access and bookkeeping should also be envisaged to optimise resource usage. In this contribution we will describe a straw man of this model, founded on basic principles such as single event level granularity for data processing and virtual data. We will explain how the current architecture will evolve adiabatically into the future distributed computing system, through the prototyping of building blocks that would be integrated in the production infrastructure as early as possible, so that specific use cases can be covered much earlier with respect to the HL-LHC time scale. We will also discuss how such system would adapt to and drive the evolution of the WLCG infrastructure in terms of facilities and services.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

SimNet: Accurate and High-Performance Computer Architecture Simulation using Deep Learning

While cycle-accurate simulators are essential tools for architecture research, design, and development, their practicality is limited by an extremely long time-to-solution for realistic applications under investigation. This work describes a concerted effort, where machine learning (ML) is used to accelerate microarchitecture simulation. First, an ML-based instruction latency prediction framework that accounts for both static instruction properties and dynamic processor states is constructed. Then, a GPU-accelerated parallel simulator is implemented based on the proposed instruction latency predictor, and its simulation accuracy and throughput are validated and evaluated against a state-of-the-art simulator. Leveraging modern GPUs, the ML-based simulator outperforms traditional CPU-based simulators significantly.

97 MATHEMATICS AND COMPUTING↗

Implementation of Relativistic Coupled Cluster Theory for Massively Parallel GPU-Accelerated Computing Architectures

In this paper, we report reimplementation of the core algorithms of relativistic coupled cluster theory aimed at modern heterogeneous high-performance computational infrastructures. The code is designed for parallel execution on many compute nodes with optional GPU coprocessing, accomplished via the new ExaTENSOR back end. The resulting ExaCorr module is primarily intended for calculations of molecules with one or more heavy elements, as relativistic effects on the electronic structure are included from the outset. In the current work, we thereby focus on exact two-component methods and demonstrate the accuracy and performance of the software. The module can be used as a stand-alone program requiring a set of molecular orbital coefficients as the starting point, but it is also interfaced to the DIRAC program that can be used to generate these. We therefore also briefly discuss an improvement of the parallel computing aspects of the relativistic self-consistent field algorithm of the DIRAC program.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

Exploring Tradeoffs in Federated Learning on Serverless Computing Architectures

Federated learning is driving the development of new techniques to efficiently and securely use data across multiple sites while using diverse resources. One of these techniques is the use of the serverless computing paradigm to abstract away resource specific configurations, allowing federated learning across heterogeneous environments. However, deploying federated learning across edge resources, the cloud, and traditional HPC sites will require specialized approaches in order to best account for the weaknesses and strengths of each resource. In this work, we explore the new tradeoffs presented by managing a federated learning task across heterogeneous resources and demonstrate these tradeoffs with experiments using a serverless federated learning framework.

Baughman, Matt↗