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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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TID testing of 4th generation iPads is reported. Of iPad subsystems, results indicate that the charging circuitry and display drivers fail at lowest TID levels. Details of construction are investigated for additional testing of components.
In 2019 the International Space Station (ISS) experienced an on on-orbit failure that affected 1 of 28 Battery Charge Discharge Units (BCDUs). Telemetry pointed to a short circuit failure of a Power Rectifier Quad Diode Module. Astronauts removed the failed unit from service which was then returned to Earth for failure analysis. The failure analysis confirmed that the quad diode module had failed short circuit. The investigation identified silver dendrites had grown on the insulated, sloped edge of the mesa semiconductor die of the failed diode and also a 2nd diode in the same quad diode module. Voids between the diode’s protective encapsulating ring and the die provided space within which dendrites were able to form and cause catastrophic failure. The NASA Engineering & Safety Center (NESC) convened a EEE Parts Sub-Team to investigate root cause and to assist with risk assessment for all of the flight diode modules (4 distinct production lots) and the flight spares (from a 5th lot). Analysis of the original diode manufacturer’s read and record screening test data identified some lots which contained diodes with parametric instabilities that could signal conditions suited for silver dendrite formation. Computed Tomography (CT) X-ray screening inspection was performed on flight spare modules to identify diodes that do not exhibit voids between the edge of die and encapsulating ring as a mitigation against dendrite formation.
The nominal performance of AEA CBPD under simulated EOS-Aqua/Aura flight hardware configuration has been demonstrated. There is no evidence of cell rupture or excessive heat production during or after CBPD switch activation under simulated high cell impedance (open-circuit cell failure mode). Inadvertent CBPD switch activation with a charged cell (low impedance path) intermittently closes and opens up the switch, therefore the device may or may not provide protection against future open-circuit cell failure. Further testing with switches F01 and F02 may provide clarification. The formation of a continuous low impedance path (a homogeneous low melting point alloy), has been confirmed - which is the expected mode of operation.
A review was made of failures and irregularities experienced on nickel cadmium batteries for 31 spacecraft. Only rarely did batteries fail completely. In many cases, poorly performing batteries were compensated for by a reduction in loads or by continuing to operate in spite of out-of-voltage conditions. Low discharge voltage was the most common problem observed in flight spacecraft (42%). Spacecraft batteries are often designed to protect against cell shorts, but cell shorts accounted for only 16% of the failures. Other causes of problems were high charge voltage (16%), battery problems caused by other elements of the spacecraft (10%), and open circuit failures (6%). Problems of miscellaneous or unknown causes occurred in 10% of the cases.
The radiation effects that affect various systems that comprise floating gate memories are presented. The wear-out degradation results of unirradiated flash memories are compared to irradiated flash memories. The procedure analyzes the failure to write and erase caused by wear-out and degradation of internal charge pump circuits. A method is described for characterizing the radiation effects of the floating gate itself. The rate dependence, stopping power dependence, SEU susceptibility and applications of floating gate in radiation environment are presented. The ramifications for dosimetry and cell failure are discussed as well as for the long term use aspects of non-volatile memories.
A self diagnostic accelerometer system has been shown to be sensitive to multiple failure modes of charge mode accelerometers. These failures include sensor structural damage, an electrical open circuit and most importantly sensor detachment. In this paper, experimental work that was performed to determine the capabilities of a self diagnostic accelerometer system while operating in the presence of various levels of mechanical noise, emulating real world conditions, is presented. The results show that the system can successfully conduct a self diagnostic routine under these conditions.
Anomalous charging currents (ACC) in polymer tantalum capacitors may appear as a temporary short circuit that can last for dozens of milliseconds, cause failures to the parts, or cause malfunctions to fast operating electronic systems. Currently, there is no standard technique or set of metrics to evaluate the level of ACC which compares results obtained by different users and manufacturers. In this work, ACC in different types of capacitors were characterized by analysis of current transients during the constant voltage ramp or power surge testing (PST) techniques. It is shown that although the shape of transients may vary at different test conditions, the transfer charge and energy remain practically the same. The level of ACC is characterized by the energy dissipated in the part during PST. Variations of the dissipated energy with moisture content, test temperature, and voltage are evaluated. Effects of different reflow soldering conditions and long-term (up to 3000 hours) storage at 125 °C are discussed.
Impedances were measured of electrodes from boiler-plate cells cycled i n KOH concentrations from 21% to 36%. These cells under accelerated conditions at 80% DOD to failure, defined discharge voltage. Cell life ranged from about 1,000 t o 40 impedances were measured at five voltages corresponding to charge. The results were analyzed using a standard circuit model including a Warburg impedance term. The kinetic resistances and Warburg slopes were greater for those electrodes which had failed earliest. Other circuit models have also been examined. The results are considered indicative but not conclusive, since the cells had been stored after failure for varying lengths of time which is known to affect the impedance. In order to minimize the effects of storage, the electrodes were cycled 10 times before the impedance measurements were taken.
Future spacecraft systems such as the manned space station will be subjected to low-dose long term radiation particles. Most electronic systems are affected by such particles. There is therefore a great need to understand device physics and failure mechanisms affected by radiation and to design circuits that would be less susceptible to radiation. Using 2 MeV electron radiation and bias temperature aging, it was found that MOS capacitors that were prepositively biased have lower flatband voltage shift and lesser increase in density of surface state charge than those that were not prepositively biased. In addition, it was shown that there is continued recovery of flatband voltage and density of state charge in irradiated capacitors during both room temperature anneal and 137 degree anneal. When nMOS transistors were subjected to 1 MeV proton radiation, charge pumping and current versus voltage measurements indicated that transconductance degradation, threshold voltage shifts and changes in interface states density may be the primary cause of nMOS transistor failure after radiation. Simulation studies using SPICE were performed on CMOS SRAM cells of various transistor sizes. It is shown that transistor sizing affects the noise margins of CMOS SRAM cells, and that as the beta ratio of the transistors of the CMOS SRAM cell decreases, the effective noise margin of the SRAM cell increases. Some suggestions were made in connection with the design of CMOS SRAMS that are hardened against single event upsets.
The real impetus for developing a production parylene coating process for internal hybrid passivation came as a result of the possibility of loose conductive particles in hybrid microelectronic circuits, causing intermittent and sometimes permanent failures. Because of the excellent mechanical properties of parylene, it is capable of securing the loose particles in place and prevent such failures. The process of coating described consists of (1) vaporizing the initial charge, which is in the form of a dimer; (2) conversion of the dimer into a reactive monomer; and (3) deposition and subsequent polymerization of the monomer in the deposition chamber which forms a uniform parylene film over all the cold surfaces in contact. Experimental results are discussed in terms of wire bond reliability, resistor drift, high-temperature storage characteristics of parylene, and coating acceptance standards. It is concluded that internal cavities of microelectronic circuits can be successfully coated with parylene provided appropriate tooling is used to protect external leads from the parylene monomer.
Recent tests at Hughes have shown that Ni/H2 cells cycled in 26 percent KOH have much longer lives than those cycled in other concentrations. As part of an ongoing program to try to correlate the impedances of nickel electrodes with their life and performance, impedances were measured of a number of electrodes from these tests that had been cycled in concentrations from 21 to 36 percent KOH. These had ranged from about 1000 to 40,000 cycles. After cycling ten times to reduce possible changes due to storage, impedances were measured at five voltages corresponding to low states of charge. The results were analyzed using a standard circuit model including Warburg impedance term. Lower kinetic resistances and Warburg slopes were found for several electrodes which had been cycled in 26 percent KOH even though they had been cycled for a much longer time than the others. Interpretation of the data is complicated by the fact that the cycle lives, storage times, and failure mechanisms varied. Several other circuit models have also been examined, but the best correlations with life were found with parameters obtained from the simple model.
The purpose of this system is to simulate an internal short on battery cells by causing deformation (a crushing force) in a cell without penetration. This is performed by activating a hydraulic cylinder on one side of a blast wall with a hydraulic pump located on the other. The operator can control the rate of the crush by monitoring a local pressure gauge connected to the hydraulic cylinder or a load cell digital display located at the hydraulic pump control area. The internal short simulated would be considered a worst-case scenario of a manufacturer fs defect. This is a catastrophic failure of a cell and could be a very destructive event. Fully charged cells are to have an internal short simulated at the center of the length of the cell (away from terminals). The crush can be performed with a .- to 1-in. (.0.6- to 2.5-cm) rod placed crossways to the cell axis, causing deformation of the cell without penetration. The OCV (open-circuit voltage) and temperature of the cells, as well as the pressure and crushing force, are recorded during the operation. Occurrence of an internal short accompanied by any visible physical changes such as venting, fires, or explosions is reported. Typical analytical data examined after the test would be plots of voltage, temperature, and pressure or force versus time. The rate of crushing force can be increased or decreased based on how fast the operator pumps the hydraulic pump. The size of cylinder used to compress the battery cell can be easily changed by adding larger or smaller fittings onto the end of the hydraulic cylinder based on the battery/cell size being tested. The cell is crushed remotely and videotaped, allowing the operator to closely monitor the situation from a safe distance.
A method has been developed for continuous cell voltage balancing for rechargeable batteries (e.g. lithium ion batteries). A resistor divider chain is provided that generates a set of voltages representing the ideal cell voltage (the voltage of each cell should be as if the cells were perfectly balanced). An operational amplifier circuit with an added current buffer stage generates the ideal voltage with a very high degree of accuracy, using the concept of negative feedback. The ideal voltages are each connected to the corresponding cell through a current- limiting resistance. Over time, having the cell connected to the ideal voltage provides a balancing current that moves the cell voltage very close to that ideal level. In effect, it adjusts the current of each cell during charging, discharging, and standby periods to force the cell voltages to be equal to the ideal voltages generated by the resistor divider. The device also includes solid-state switches that disconnect the circuit from the battery so that it will not discharge the battery during storage. This solution requires relatively few parts and is, therefore, of lower cost and of increased reliability due to the fewer failure modes. Additionally, this design uses very little power. A preliminary model predicts a power usage of 0.18 W for an 8-cell battery. This approach is applicable to a wide range of battery capacities and voltages.
Topics include: Wearable Environmental and Physiological Sensing Unit; Broadband Phase Retrieval for Image-Based Wavefront Sensing; Filter Function for Wavefront Sensing Over a Field of View; Iterative-Transform Phase Retrieval Using Adaptive Diversity; Wavefront Sensing With Switched Lenses for Defocus Diversity; Smooth Phase Interpolated Keying; Maintaining Stability During a Conducted-Ripple EMC Test; Photodiode Preamplifier for Laser Ranging With Weak Signals; Advanced High-Definition Video Cameras; Circuit for Full Charging of Series Lithium-Ion Cells; Analog Nonvolatile Computer Memory Circuits; JavaGenes Molecular Evolution; World Wind 3D Earth Viewing; Lithium Dinitramide as an Additive in Lithium Power Cells; Accounting for Uncertainties in Strengths of SiC MEMS Parts; Ion-Conducting Organic/Inorganic Polymers; MoO3 Cathodes for High-Temperature Lithium Thin-Film Cells; Counterrotating-Shoulder Mechanism for Friction Stir Welding; Strain Gauges Indicate Differential-CTE-Induced Failures; Antibodies Against Three Forms of Urokinase; Understanding and Counteracting Fatigue in Flight Crews; Active Correction of Aberrations of Low-Quality Telescope Optics; Dual-Beam Atom Laser Driven by Spinor Dynamics; Rugged, Tunable Extended-Cavity Diode Laser; Balloon for Long-Duration, High-Altitude Flight at Venus; and Wide-Temperature-Range Integrated Operational Amplifier.
Electrochemical impedance spectra of rolled and bonded and sintered porous nickel battery electrodes were recorded periodically during charge/discharge cycling in concentrated KOH solution at various temperatures. A transmission line model (TLM) was adopted to represent the impedance of the porous electrodes, and various model parameters were adjusted in a curve fitting routine to reproduce the experimental impedances. Degradation processes for rolled and bonded electrodes were deduced from changes in model parameters with electrode cycling time. In developing the TLM, impedance spectra of planar (non-porous) electrodes were used to represent the pore wall and backing plate interfacial impedances. These data were measured over a range of potentials and temperatures, and an equivalent circuit model was adopted to represent the planar electrode data. Cyclic voltammetry was used to study the characteristics of the oxygen evolution reaction on planar nickel electrodes during charging, since oxygen evolution can affect battery electrode charging efficiency and ultimately electrode cycle life if the overpotential for oxygen evolution is sufficiently low. Transmission line modeling results suggest that porous rolled and bonded nickel electrodes undergo restructuring during charge/discharge cycling prior to failure.
The single event effects or phenomena (SEP), which so far have been observed as events falling on one or another of the SE classes: Single Event Upset (SEU), Single Event Latchup (SEL) and Single Event Burnout (SEB), are examined. Single event upset is defined as a lasting, reversible change in the state of a multistable (usually bistable) electronic circuit such as a flip-flop or latch. In a computer memory, SEUs manifest themselves as unexplained bit flips. Since latchup is in general caused by a single event of short duration, the single event part of the SEL term is superfluous. Nevertheless, it is used customarily to differentiate latchup due to a single heavy charged particle striking a sensitive cell from more ordinary kinds of latchup. Single event burnout (SEB) refers usually to total instantaneous failure of a power FET when struck by a single particle, with the device shorting out the power supply. An unforeseen failure of these kinds can be catastrophic to a space mission, and the possibilities are discussed.
Implanted electronic devices are typically powered by batteries or transcutaneous power transmission. Batteries must be replaced or recharged, and transcutaneous power sources burden the patient or subject with external equipment prone to failure. A completely self-sustaining implanted power source would alleviate these limitations. Skeletal muscle provides an available autologous power source containing native chemical energy that produces power in excess of the requirements for muscle activation by motor nerve stimulation. A concept has been developed to convert stimulated skeletal muscle power into electrical energy (see the preceding illustration). We propose to connect a piezoelectric generator between a muscle tendon and bone. Electrically stimulated muscle contractions would exert force on the piezoelectric generator, charging a storage circuit that would be used to power the stimulator and other devices.
The phase-locked loop (PLL) is an old and widely used circuit for frequency and phase demodulation, carrier and clock recovery, and frequency synthesis [1]. Its implementations range from discrete components to fully integrated circuits and even to firmware or software. Often the PLL is a highly critical component of a system, as for example when it is used to derive the on-chip clock, but as of this writing no definitive single-event upset (SET)/single-event transient (SET) tolerant PLL circuit has been described. This chapter hopes to rectify that situation, at least in regard to PLLs that are used to generate clocks. Older literature on fault-tolerant PLLs deals with detection of a hard failure, which is recovered by replacement, repair, or manual restart of discrete component systems. Several patents exist along these lines (6349391, 6272647, and 7089442). A newer approach is to harden the parts of a PLL system, to one degree or another, such as by using a voltage-based charge pump or a triple modular redundant (TMR) voted voltage-controlled oscillator (VCO). A more comprehensive approach is to harden by triplication and voting (TMR) all the digital pieces (primarily the divider) of a frequency synthesis PLL, but this still leaves room for errors in the VCO and the loop filter. Instead of hardening or voting pieces of a system, such as a frequency synthesis system (i.e., clock multiplier), we will show how the entire system can be voted. There are two main ways of doing this, each with advantages and drawbacks. We will show how each has advantages in certain areas, depending on the lock acquisition and tracking characteristics of the PLL. Because of this dependency on PLL characteristics, we will briefly revisit the theory of PLLs. But first we will describe the characteristics of voters and their correct application, as some literature does not follow the voting procedure that guarantees elimination of errors. Additionally, we will find that voting clocks is a bit trickier than voting data where an infallible clock is assumed. It is our job here to produce (or recover) that assumed infallible clock!