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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1986

Solenoid-Simulation Circuit

Electrical properties of solenoids imitated for tests of control circuits. Simulation circuit imitates voltage and current responses of two engine-controlling solenoids. Used in tests of programs of digital engine-control circuits, also provides electronic interface with circuits imitating electrical properties of pressure sensors and linear variable-differential transformers. Produces voltages, currents, delays, and discrete turnon and turnoff signals representing operation of solenoid in engine-control relay. Many such circuits used simulating overall engine circuitry.

Simon, R. A.↗
NASA NTRSDate not supplied

Incorporating ADAPT-VQE with a Sparse Wavefunction Circuit Simulator to Find Compact Quantum Circuits for Chemical Applications

We implemented the ADAPT-VQE algorithm into our recent classical sparse wavefunction circuit simulator to demonstrate that classical resources can (1) efficiently find a physically motivated compact wavefunction ansatz for further refinement on near-term quantum hardware and (2) benchmark expected results of VQE-based algorithms once the quantum hardware is available to study large-scale applications. In particular, we study the role of the ADAPT-VQE operator pool, molecular basis set selection, and variations such as TETRIS-ADAPT-VQE on the performance of our classical circuit simulator. This work demonstrates the promise of using classical resources to generate highly accurate wavefunctions that can be prepared on quantum hardware to initiate other quantum algorithms such as phase estimation. Our approach harnesses the power of high-performance computing resources with the more limited available quantum computers to map a path toward quantum advantage for electronic structure calculations in chemistry and materials science.

Quantum Computing↗
NASA NTRS1984

VLSI circuit simulation using a vector computer

Simulation of circuits having more than 2000 active devices requires the largest, fastest computers available. A vector computer, such as the CYBER 205, can yield great speed and cost advantages if efforts are made to adapt the simulation program to the strengths of the computer. ASPEC and SPICE (1), two widely used circuit simulation programs, are discussed. ASPECV and VAMOS (5) are respectively vector adaptations of these two simulators. They demonstrate the substantial performance enhancements possible for this class of algorithm on the CYBER 205.

Mcgrogan, S. K.↗
NASA NTRS1991

A study of ignition and simulation circuits for arcjet thrusters, part 1

A 1 kW electronic load was programmed to simulate the nonlinear i-v (volt-ampere) characteristics of an arcjet, both ignited and unignited. The simulator was tested and found to closely resemble an arcjet both for large transients and small perturbances up to about 40 kHz. No attempt was made to simulate the ignition process itself. The dynamic behavior of the arcjet (and the simulator) was shown to differ significantly from that of a resistor bank. Previous research led to the design and construction of a 1 kW arcjet power supply. A high voltage ignition circuit was added to this hardware, and tests on a 1 kW arcjet were performed at NASA-Lewis. All tests were successful and no ignition failures were observed. Circuit documentation and test results are included.

Stuart, Thomas A.↗
NASA NTRS1984

Bipolar junction transistor models for circuit simulation of cosmic-ray-induced soft errors

This paper examines bipolar junction transistor models suitable for calculating the effects of large excursions of some of the variables determining the operation of a transistor. Both the Ebers-Moll and Gummel-Poon models are studied, and the junction and diffusion capacitances are evaluated on the basis of the latter model. The most interesting result of this analysis is that a bipolar junction transistor when struck by a cosmic particle may cause a single event upset in an electronic circuit if the transistor is operated at a low forward base-emitter bias.

Benumof, R.↗
NASA NTRS1977

Device model for FETSIM circuit simulation program

A description of the MOS transistor used in the FETSIM analysis program is presented. CMOS/SOS device parameters are included. Typical device mobilities are given as well as the empirically determined constants necessary to model second-order effect conductance variations due to gate voltage and saturated drain voltage.

Ramondetta, P.↗
NASA NTRS1987

Pressure-Transducer Simulator

Simulation circuit operates under remote, automatic, or manual control to produce electrical outputs similar to pressure transducer. Specific circuit designed for simulations of Space Shuttle main engine. General circuit concept adaptable to other simulation and control systems involving several operating modes. Switches and amplifiers respond to external control signals and panel control settings to vary differential excitation of resistive bridge. Output voltage or passive terminal resistance made to equal pressure transducer in any of four operating modes.

Simon, Richard A.↗
NASA NTRS1988

Integrated Circuit For Simulation Of Neural Network

Ballast resistors deposited on top of circuit structure. Cascadable, programmable binary connection matrix fabricated in VLSI form as basic building block for assembly of like units into content-addressable electronic memory matrices operating somewhat like networks of neurons. Connections formed during storage of data, and data recalled from memory by prompting matrix with approximate or partly erroneous signals. Redundancy in pattern of connections causes matrix to respond with correct stored data.

Thakoor, Anilkumar P.↗
NASA NTRS1993

The role of simulation in the design of a neural network chip

An iterative, simulation-based design procedure for a neural network chip is introduced. For this design procedure, the goal is to produce a chip layout for a neural network in which the weights are determined by transistor gate width-to-length ratios. In a given iteration, the current layout is simulated using the circuit simulator SPICE, and layout adjustments are made based on conventional gradient-decent methods. After the iteration converges, the chip is fabricated. Monte Carlo analysis is used to predict the effect of statistical fabrication process variations on the overall performance of the neural network chip.

Desai, Utpal↗
NASA NTRS1985

Single-Event Upset (SEU) model verification and threshold determination using heavy ions in a bipolar static RAM

Single-Event Upset (SEU) response of a bipolar low-power Schottky-diode-clamped TTL static RAM has been observed using Br ions in the 100-240 MeV energy range and O ions in the 20-100 MeV range. These data complete the experimental verification of circuit-simulation SEU modeling for this device. The threshold for onset of SEU has been observed by the variation of energy, ion species and angle of incidence. The results obtained from the computer circuit-simulation modeling and experimental model verification demonstrate a viable methodology for modeling SEU in bipolar integrated circuits.

Zoutendyk, J. A.↗
NASA NTRS1995

Ring-plane traveling-wave tube slow-wave circuit design simulations at V-Band frequencies

The V-Band frequency range of 59-64 GHz is a region of the millimeter-wave spectrum that has been designated for intersatellite communications. As a first effort to develop a high-efficiency V-band TWT, variations on a ring-plane slow-wave circuit were computationally investigated to develop an alternative to the more conventional ferruled coupled-cavity circuit. The ring-plane circuit was chosen because of its high interaction impedance, large beam aperture, and excellent thermal dissipation properties. Despite the high-power capabilities of the ring-plane TWT, disadvantages of low bandwidth and high voltage requirements have until now prevented its acceptance outside the laboratory. In this paper, we use the three-dimensional electromagnetic simulation code MAFIA to investigate methods of increasing the bandwidth and lowering the operating voltage. Dispersion, impedance, and attenuation calculations for various geometric variations and loading distributions were performed. Based on the results of the variations, a circuit termed the finned-ladder TWT slowwave circuit was designed and is compared here to the scaled ring-plane prototype and the conventional ferruled coupled-cavity TWT circuit over the V-band frequency range.

Kory, Carol L.↗
NASA NTRS2013

Memory Circuit Fault Simulator

Spacecraft are known to experience significant memory part-related failures and problems, both pre- and postlaunch. These memory parts include both static and dynamic memories (SRAM and DRAM). These failures manifest themselves in a variety of ways, such as pattern-sensitive failures, timingsensitive failures, etc. Because of the mission critical nature memory devices play in spacecraft architecture and operation, understanding their failure modes is vital to successful mission operation. To support this need, a generic simulation tool that can model different data patterns in conjunction with variable write and read conditions was developed. This tool is a mathematical and graphical way to embed pattern, electrical, and physical information to perform what-if analysis as part of a root cause failure analysis effort.

Sheldon, Douglas J.↗
NASA NTRSDate not supplied

Surrogate Optimization for Quantum Circuits

Variational quantum Eigensolvers are touted as a near-term algorithm capable of impacting many applications. However, the potential has yet to be realized with few claims of quantum advantage and high resource estimates mainly due to the need for optimization in the presence of noise. Finding algorithms and methods to improve the convergence is essential to accelerate the capabilities of near-term hardware for VQE or more broad applications of hybrid methods in which optimization is required. To this goal we look to use modern approaches recently developed in circuit simulations and stochastic classical optimization that can be combined in a surrogate optimization approach to classical circuits. Using an approximate state vector simulator, we efficiently calculate an approximate Hessian, fed as an input for a detailed quantum circuit simulator. We demonstrate the capabilities of such an approach with and without sampling noise. We also show that this method outperforms Powell in the presence of quantum circuit shot noise by a factor of 2-4

quantum computing↗
NASA NTRS2025

Design and Simulation of Greatly Improved Future Generation 4H-SiC JFET-R Integrated Circuits for Prolonged 500 °C Operation

This work compares design layouts and circuit simulations of the next two prototype NASA Glenn SiC JFET-R IC fabrication runs designated “IC Gen. 12” and “IC Gen. 13”. Even though both generations employ the same physical JFET gate length and chip size, SPICE simulations predict drastic improvements to IC capabilities and performance metrics for Gen. 13 over Gen. 12. The main factors behind simulated performance differences are thinner n-channel layer leading to reduced operating voltages and switch to stepper-based photolithography that enables roughly 4-fold layout area reductions for functionally identical circuit blocks.

Silicon Carbide↗
NASA NTRS2001

Electronic Model of a Ferroelectric Field Effect Transistor

A pair of electronic models has been developed of a Ferroelectric Field Effect transistor. These models can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The models use the Schmitt trigger circuit as a basis for their design. One model uses bipolar junction transistors and one uses MOSFET's. Each model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current from each model has similar values to an actual FFET that was measured experimentally. T'he input and o Output resistance in the models are also similar to that of the FFET. The models are valid for all frequencies below RF levels. No attempt was made to model the high frequency characteristics of the FFET. Each model can be used to design circuits using FFET's with standard electrical simulation packages. These circuits can be used in designing non-volatile memory circuits and logic circuits and is compatible with all SPICE based circuit analysis programs. The models consist of only standard electrical components, such as BJT's, MOSFET's, diodes, resistors, and capacitors. Each model is compared to the experimental data measured from an actual FFET.

MacLeod, Todd C.↗
NASA NTRS2013

Planar Superconducting Millimeter-Wave/Terahertz Channelizing Filter

This innovation is a compact, superconducting, channelizing bandpass filter on a single-crystal (0.45 m thick) silicon substrate, which operates from 300 to 600 GHz. This device consists of four channels with center frequencies of 310, 380, 460, and 550 GHz, with approximately 50-GHz bandwidth per channel. The filter concept is inspired by the mammalian cochlea, which is a channelizing filter that covers three decades of bandwidth and 3,000 channels in a very small physical space. By using a simplified physical cochlear model, and its electrical analog of a channelizing filter covering multiple octaves bandwidth, a large number of output channels with high inter-channel isolation and high-order upper stopband response can be designed. A channelizing filter is a critical component used in spectrometer instruments that measure the intensity of light at various frequencies. This embodiment was designed for MicroSpec in order to increase the resolution of the instrument (with four channels, the resolution will be increased by a factor of four). MicroSpec is a revolutionary wafer-scale spectrometer that is intended for the SPICA (Space Infrared Telescope for Cosmology and Astrophysics) Mission. In addition to being a vital component of MicroSpec, the channelizing filter itself is a low-resolution spectrometer when integrated with only an antenna at its input, and a detector at each channel s output. During the design process for this filter, the available characteristic impedances, possible lumped element ranges, and fabrication tolerances were identified for design on a very thin silicon substrate. Iterations between full-wave and lumped-element circuit simulations were performed. Each channel s circuit was designed based on the availability of characteristic impedances and lumped element ranges. This design was based on a tabular type bandpass filter with no spurious harmonic response. Extensive electromagnetic modeling for each channel was performed. Four channels, with 50-GHz bandwidth, were designed, each using multiple transmission line media such as microstrip, coplanar waveguide, and quasi-lumped components on 0.45- m thick silicon. In the design process, modeling issues had to be overcome. Due to the extremely high frequencies, very thin Si substrate, and the superconducting metal layers, most commercially available software fails in various ways. These issues were mitigated by using alternative software that was capable of handling them at the expense of greater simulation time. The design of on-chip components for the filter characterization, such as a broadband antenna, Wilkinson power dividers, attenuators, detectors, and transitions has been completed.

Ehsan, Negar↗
NASA NTRS1984

Soft-error generation due to heavy-ion tracks in bipolar integrated circuits

Both bipolar and MOS integrated circuits have been empirically demonstrated to be susceptible to single-particle soft-error generation, commonly referred to as single-event upset (SEU), which is manifested in a bit-flip in a latch-circuit construction. Here, the intrinsic characteristics of SEU in bipolar (static) RAM's are demonstrated through results obtained from the modeling of this effect using computer circuit-simulation techniques. It is shown that as the dimensions of the devices decrease, the critical charge required to cause SEU decreases in proportion to the device cross-section. The overall results of the simulations are applicable to most integrated circuit designs.

Zoutendyk, J. A.↗