A comparison of binary delay-lock tracking-loop implementations.
Binary delay-lock tracking-loop performance for various RF implementations
PHASE DETECTOR↗
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Delay-locked-loop timing error mitigation
Systems, methods, and circuits provide delay-locked loop (DLL) timing error mitigation. A DLL false-lock detection system can include DLL circuitry configured to receive a reference clock signal having a time period. The system can include shift register circuitry and latched comparison circuitry which can determine a time period of a locked condition of the DLL delay line with respect to the reference clock signal time period. The system can determine whether the system is correctly locked to the base time period or incorrectly locked to a multiple of the base time period. A further system can operate to cause a phase detector circuitry in a DLL to ignore the first edge of a reference clock signal presented to the phase detector circuitry and thereby avoid stuck-lock conditions.
Filippini, Leo↗
Delay-lock-loop code-correlation synchronizer
Temperature dependence and sensitivity to noise are greatly reduced in system designed to process biphase-level pulse-code-modulated signals.
Pardoe, C. T.↗
Delay-lock techniques for the AROD system, volume 2
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Ward, R. B.↗
On optimal signals for phase-locked loops
Optimum signals for phase locked or delay locked loops determined as function of signal to noise ratio
Layland, J. W.↗
Noncoherent pseudonoise code tracking performance of spread spectrum receivers
The optimum design and performance of two noncoherent PN tracking loop configurations, namely, the delay-locked loop and tau-dither loop, are described. In particular, the bandlimiting effects of the bandpass arm filters are considered by demonstrating that for a fixed data rate and data signal-to-noise ratio, there exists an optimum filter bandwidth in the sense of minimizing the loop's tracking jitter. Both the linear and nonlinear loop analyses are presented, and the region of validity of the former relative to the latter is indicated. In addition, numerical results are given for several filter types. For example, assuming ideal bandpass arm filters, it is shown that the tau-dither loop requires approximately 1 dB more signal-to-noise ratio than the delay-locked loop for equal rms tracking jitters.
Simon, M. K.↗
High dynamic, low volume GPS receiver
A new GPS receiver concept and design are presented to meet the high dynamic and low volume requirements for range applications in missiles and drones. The receiver has the potential to satisfy all range requirements with one basic receiver, which has significant potential economic benefit over the alternate approach of using a family of receivers, each tailored for specific applications. The main new concept is to use approximate maximum likelihood estimates of pseudo range and range-rate, rather than tracking with carrier phase locked loops and code delay locked loops. Preliminary analysis indicates that receivers accelerating at 50 g or more can track with position errors due to acceleration of approximately 0.2 m/g, or 10 m at 50 g. Implementation is almost entirely digital to meet the low volume requirements.
Hurd, W. J.↗
Deconvolution Approach to Carrier and Code Multipath Error Elimination in High Precision GPS
This paper proposes a novel technique based on the deconvolution approach of the simultaneous estimation and compensation of the multipath estimation errors in both the carrier phase lock and the code delay lock loops in GPS receivers. Simulation results are presented showing that the proposed GPS receiver algorithm achieves high precision in the range and differential range estimation in various GPS precision applications such as spacecraft attitude control, even in a relatively severe multipath environment.
GPS↗
A unified analysis of pseudonoise synchronization by envelope correlation
A relationship between coarse acquisition (coarse alignment of two pseudonoise codes to within approximately one code symbol) and fine acquisition (tracking) in a pseudonoise modulated spread spectrum communication system is studied. A convenient technique for determining mean acquisition time and hold-in time (mean time to lose lock) after acquisition, using a delay lock loop, is elaborated. An analysis procedure for handling the transition from search to lock is developed and applied to a problem containing representative Space Shuttle data (signal parameters and synchronizer parameters).
Hopkins, P. M.↗
PN lock indicator for dithered PN code tracking loop
In a delay-lock one-delta (+or - 1/2 chip) dithered PN code tracking loop, an indication of lock in the PN code tracking loop is provided by delaying the dithered local PN code by a half chip to produce a +0, -1 dithered PN code that is then multiplied with the received PN-spread IF signal to produce a signal proportional to the correlation of this dithered code offset from the received code. The correlation signal is bandpass filtered, amplified with AGC control, and square-law detected to obtain a dc signal proportional to the degree of correlation. The dc signal is multiplied by the dithering control signal to effectivity substract noise voltage from the lock correlation signal which is then compared with a PN lock status signal.
Carson, L. M.↗
Instrumentation for one-way satellite PTTI applications
A review of general principles and operational procedures illustrates how the typical passive user and omni receiving antenna can recover Precise Time and Time Interval (PTTI) information from a low altitude navigation satellite system for clock calibration and synchronization. Detailed discussions of concepts and theory of the receiver design are presented. The importance of RF correlation of the received and local PN encoded sequences is emphasized as a means of reducing delay uncertainties of the instrumentation to values compatible with nanosecond to submicrosecond PTTI objectives. Two receiver configurations were fabricated for use in satellite-to-laboratory experiments. In one receiver the delay-locked loop for PN signals synchronization used a dithered amplitude detection process while the second receiver used a complex sums phase detection method for measurement of delay error. The necessity for compensation of Doppler shift is discussed. Differences in theoretical signal acquisition and tracking performance of the design concepts are noted.
Osborne, A. E.↗
Spread spectrum acquisition and tracking performance for Shuttle communication links
The spread spectrum acquisition and tracking performance for the Shuttle S-band and Ku-band communication links are analyzed and compared to test results. The S-band link requirements are more severe than those of the Ku-band links, hence, different despreader designs were developed for the two systems. The S-band despreader acquires pseudonoise code lock by examining all possible code phases in half chip steps while the Ku-band despreader acquires pseudonoise code lock by continuously sweeping a tau-jitter loop. Both despreaders employ a tau-jitter loop for code tracking. The code tracking performance is computed for the tau-jitter loop and compared to that of the more complex delay lock loop.
Alem, W. K.↗
A high-resolution clock phase shifter circuitry for ALTIROC
Abstract A high-resolution clock phase shifter is implemented to adjust the phase of multiple clocks at 40 MHz, 80 MHz, or 640 MHz in the ALTIROC chip. The phase shifter has a coarse-phase shifter and a fine-phase shifter to achieve a step size of 97.7 ps and an adjustable range of 25 ns. The fine delay unit is based on a Delay Locked Loop (DLL) operating at 640 MHz. The phase shifter is fabricated in a 130 nm CMOS process. The area of the phase shifter is 725 µm × 248 µm. The Differential Non-Linearity (DNL) and the Integral Non-Linearity (INL) are ±0.6 LSB and ±0.75 LSB, respectively. The jitter from −25 °C to 20 °C is less than 15.5 ps (RMS), including the contributions from the FPGA clock source and the PLL. The power consumption is 11.2 mW.
Instruments & Instrumentation↗
A Low-Power 1 Gb/s Line Driver with Configurable Pre-Emphasis for Lossy Transmission Lines
A line driver with configurable pre-emphasis is implemented in a 65 nm CMOS process. The driver utilizes a three-tap feed-forward equalization (FFE) architecture. The relative delays between the taps are selectable in increments of 1/16th of the unit interval (UI) via an 8-stage delay-locked loop (DLL) and digital interpolator. It is also possible to control the output amplitude and source impedance for each tap via a programmable array of eight source-series terminated (SST) drivers. The entire design consumes 9 mW from a 1.2 V supply at 1 Gb/s.
47 OTHER INSTRUMENTATION↗
AstroPix4 — a novel HV-CMOS sensor developed for space based experiments
For the proposed space based gamma-ray observatory All-sky Medium-Energy Gamma-ray Observatory eXplorer (AMEGO-X), a silicon tracker based on a novel High Voltage-CMOS (HV-CMOS) sensor called AstroPix, is currently being developed. Preliminary measurements with the first full reticle prototype AstroPix3 show that the power target of 1.5 mW/cm 2 can currently not be reached due to the digital consumption of 3.08 mW/cm 2 , while the analog power consumption of 1.04 mW/cm 2 and a break down voltage of over 350 V look promising. Based on these results, the design changes in AstroPix4, submitted in May 2023, are presented, containing changes to the time stamp generation and readout architecture. A digital power consumption below 0.25 mW/cm 2 is expected by removing the fast 200 MHz clock used to measure the time-over-threshold (ToT) and an LVDS receiver. A maximum resolution of 3.125 ns for time-of-arrival (ToA) and ToT is reached by adding per-pixel Flash-Time-to-Digital Converter (TDCs) controlled by a global delay-locked loop (DLL).
47 OTHER INSTRUMENTATION↗
A new approach to lightweight radar altimeters
Test results and key principles are given for a radar altimeter designed for meteorological balloons. The instrument, which weighs 160 g and consumes 0.7 W, will fill a gap in meteorological sensing using balloons - an area where pressure altitude was formerly the prevailing reference. The instrument is basically a delay-lock radar utilizing a superregenerative RF stage. Long-term absolute accuracy of plus or minus 10 m and short-term stability of better than 2 m rms were measured at altitudes of 20 km.
Levanon, N.↗
Carrier and symbol synchronization system performance study
Results pertinent to predicting the performance of convolutionally encoded binary phase-shift keyed communication links were presented. The details of the development are provided in four sections. These sections are concerned with developing the bit error probability performance degradations due to PN despreading by a time-shared delay locked loop, the Costas demodulation process, symbol synchronization effects and cycle slipping phenomena in the Costas loop. In addition, Costas cycle slipping probabilities are studied as functions of Doppler count time and signal-to-noise conditions. The effect of cycle slipping in the symbol synchronizer is also studied as a function of channel Doppler and other frequency uncertainties.
Lindsey, W. C.↗
Double dither loop for pseudonoise code tracking
A new type of phase detector for pseudonoise code tracking is introduced and analyzed in comparison with the delay lock loop (DLL) and tau-dither loop (TDL) configurations. It is shown that the double dither loop (DDL) combines the best features of the DLL and the TDL in that the DDL is insensitive to gain and offset imbalances and does not suffer the 3-dB degradation in noise performance typically associated with the TDL. The double dither concept is applicable to other dual channel detectors such as in a Costas-type carrier tracking loop.
Hopkins, P. M.↗