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Modern high-performance radar systems are employing ever-more Digital Signal Processing (DSP), replacing ever-more formerly analog components. Precisely predicting the performance of digital filters and correlators requires an awareness of some of the finer points and characteristics of digital filters. We examine a representative radar receiver DSP chain that is processing a Linear Frequency Modulated (LFM) chirp.
Reducing costs and increasing manufacturing output while creating reliable products are three essential components needed to keep a business competitive. In the past, having an asset that could address these three challenges at the same time would be challenging. However, recent advances in computer processing capabilities coupled with increases to network speeds allowed such a system to become possible; and this is known as a Digital Twin (DT), which represents a virtual copy of a production system or a product. Here, this work exhibits a DT application of an Active Neutral Point Clamped (ANPC) inverter using a controller. The controller emulates the ANPC responses of a new Digital Signal Processing (DSP) firmware and validates this new firmware by using Design-For-Trust (DFTr) characteristics. If the new firmware is malicious, then it should be rejected, thus adding preemptive protection measures for inverter based distributed energy resources.
Perovskite‐based direct radiation detectors offer a compelling platform for room‐temperature gamma spectroscopy due to their high sensitivity, tunable optoelectronic properties, and compatibility with solution processing. While prior studies on formamidinium lead tribromide (FAPbBr 3 ) have shown that surface passivation mitigates deep trap state impact on the charge collection efficiency (CCE), the influence of surface‐based shallow traps on time‐resolved detector response remains largely unexplored. In this article, a digital signal processing (DSP) method is applied to analyze waveform rising edge dynamics in FAPbBr 3 single‐crystal detectors, identifying prompt and delayed charge collection components. Using the second derivative of the collected charge signal, the onset of shallow trap reemission is isolated, occurring 1.1 µs after carrier generation. Surface passivation suppressed deep trap states, shifting carrier occupancy toward shallower traps and extending the temporal window of delayed charge collection. This delayed contribution correlates with measurable changes in the temporal and amplitude distributions of detector events. By leveraging time‐domain filtering informed by these dynamics, a selective enhancement in signal quality and gamma peak‐to‐Compton ratio (PCR) is achieved, while preserving over 90% of photoelectric events. An improvement in the PCR to 1.80, from the original 1.09, is enabled by focusing on high collection efficiency events corresponding to reemitted carriers in the 1.1 to 3 µs range after the generation event. These results demonstrate a pathway for leveraging shallow trap dynamics to enhance spectral fidelity in time‐resolved perovskite detectors.
We report the first O-band link with electrically reconfigurable intensity-modulation direct-detection (IMDD) and coherent operation using custom silicon photonic chips packaged with commercial electronic chips. Transmission below the KP4-FEC threshold is shown using commercial 53 Gbaud PAM4 digital signal processing (DSP) for 16QAM (200 Gbps/ λ ) and PAM4 (100 Gbps/ λ ). Efficient operation of the packaged full link at 12 and 11.2 pJ/bit is achieved for the PAM4 and 16QAM modes, respectively.
Currently there is great interest in the utility of deep neural networks (DNNs) for the physical layer of radio frequency (RF) communications. In this manuscript we describe a custom DNN specially designed to solve problems in the RF domain. Our model leverages the mechanisms of feature extraction and attention through the combination of an autoencoder convolutional network with a transformer network, to accomplish several important communications network and digital signals processing (DSP) tasks. We also present a new open dataset and physical data augmentation model that enables training of DNNs that can perform automatic modulation classification, infer, and correct transmission channel effects, and directly demodulate baseband RF signals.
We introduce a technique to mitigate the effects of low frequency noise on precision timing. The example of Dark Count Noise Rate (DCR) in Silicon Photomultipliers (SiPMs) is emphasized. This technique exploits the correlation between time shifts on the leading edge of a signal and the residual slope of the baseline (due to noise) which remains after baseline subtraction. In fast timing applications (such as for Time-of-flight particle ID) the signal arrival time is typically captured on the signal leading edge. The signal risetime is often fixed by the physics of the sensor and input circuit. Then accurate pulse timing can be achieved by correcting a leading edge threshold time (depending on a slope proportional to both the Amplitude and the risetime) to a “constant fraction” time. This compensation for time walk due to amplitude fluctuations breaks down once we introduce interference from low frequency noise on the leading edge. In this paper we demonstrate that an additional measurement of the slope at threshold can be used to correct for this noise jitter.
The SuperCDMS SNOLAB dark matter search experiment aims to be sensitive to energy depositions down to Script O(1 eV). This imposes requirements on the resolution, signal efficiency, and noise rejection of the trigger system. To accomplish this, the SuperCDMS level-1 trigger system is implemented in an FPGA on a custom PCB. A time-domain optimal filter algorithm realized as a finite impulse response filter provides a baseline resolution of 0.38 times the standard deviation of the noise, σn, and a 99.9% trigger efficiency for signal amplitudes of 1.1 σ n in typical noise conditions. Embedded in a modular architecture, flexible trigger logic enables reliable triggering and vetoing in a dead-time-free manner for a variety of purposes and run conditions. The trigger architecture and performance are detailed in this article.
A line driver with configurable pre-emphasis is implemented in a 65 nm CMOS process. The driver utilizes a three-tap feed-forward equalization (FFE) architecture. The relative delays between the taps are selectable in increments of 1/16th of the unit interval (UI) via an 8-stage delay-locked loop (DLL) and digital interpolator. It is also possible to control the output amplitude and source impedance for each tap via a programmable array of eight source-series terminated (SST) drivers. The entire design consumes 9 mW from a 1.2 V supply at 1 Gb/s.
Here, this paper details the implementation of the digital pulse shaping subsystem within the Backbone Transmission Line Encoding (BTLE) driver, a low-power, long-distance on-chip data transmission solution designed in a 65 nm CMOS process. Digital pulse shaping is critical for minimizing inter-symbol interference (ISI) caused by bandwidth limitations of on-chip interconnects, especially in wafer-scale monolithic active pixel sensors (MAPS). A duobinary encoder coupled with a parallelized polyphase finite impulse response (FIR) filter is used for efficient shaping of the transmitted signal spectrum. This reconfigurable architecture achieves reliable 160 Mb/s data transfer over a 10 cm on-chip link, as validated by simulations demonstrating low power consumption (FoM 37.3 fJ/bit/mm of transmission line length) and effective ISI mitigation.
For LHC Run 3, the ALICE Time Projection Chamber was upgraded to operate in continuous readout mode. Interaction rates of up to 50 kHz in Pb-Pb collisions require real-time processing of more than 3 TB s -1 of raw detector data. This requirement is met by a custom FPGA-based processing pipeline that performs the complete front-end data treatment fully in-stream, including common-mode correction, pedestal subtraction, ion-tail filtering, zero suppression, and dense data packing. A central element of the design is a highly parallel common-mode correction algorithm operating directly on the streaming data. It robustly identifies signal-free readout channels on a time-bin basis and applies pad-dependent scaling to compensate for local variations in capacitive coupling in the GEM readout. In combination with pedestal subtraction and ion-tail filtering, this enables accurate baseline restoration under extreme high-occupancy conditions, preventing signal loss while efficiently suppressing noise prior to zero suppression. The pipeline operates continuously at the full detector bandwidth and reduces the raw input rate of approximately 3 TB s -1 to about 900 GBps for Pb-Pb collisions at the target interaction rate. Overall, it represents a large-scale FPGA-based real-time signal-processing implementation for high-energy physics detector readout.
High-fidelity electromagnetic transient (EMT) simulation plays a critical role in understanding the dynamic behavior and fast transients involved in operation, control, and protection of Multi-Terminal dc (MTdc) grids. Here, this paper proposes a cost-effective high-performance real-time EMT simulation platform for large-scale cross-continental MTdc grids based on graphics processing unit (GPU). The proposed simulation platform: i) assembles detailed EMT models of all components within an MTdc-ac grid into a single platform. This setup provides a complete simulation solution to capture fast transient signals required for high-bandwidth controller design and protection studies without any compromise; ii) implements the first GPU-based simulation architecture and corresponding algorithms for MTdc-ac grids with real-time performance at scales of 1s; iii) is highly-efficient and balances the high utilization of GPU resources and low latency required for the simulation; and iv) outperforms the existing central processing unit (CPU)- or digital signal processor (DSP)/field-programmable gate array (FPGA)-based simulators in terms of its higher scalability on large-scale MTdc-ac grids and superior price-performance ratio on the hardware. Accuracy and performance of the proposed platform are evaluated with respect to the reference results from PSCAD/EMTDC environment.
The demand for renewable energy has increased over the last few years, and so has the demand for greater expectations within the energy market. This increasing trend has been accompanied by more significant usage of internet-connected devices (IoT), leading to critical electrical infrastructure being connected to the internet. Implementing internet connectivity with such devices and systems provides benefits such as improving the system's performance, facilitating irregularity and anomaly mitigation, and providing additional situational awareness for enhanced decision-making. However, enhancing the connected system with IoT introduces a drawback – a greater vulnerability to cyber-attacks. Cyber-attacks targeting critical infrastructure in the electrical sector have occurred in the United States and Ukraine. These cyber-attacks highlight and expose vulnerabilities that a system inherits when connecting to the internet. These attacks left thousands of customers without electricity for hours until operators could regain control of the electric utility grid. Therefore, to address the vulnerabilities of an internet-connected power electronic device, this work focused on the hardware layer of the system. Implementing a cyber-control system inside the hardware layer can significantly reduce the possibility of an attacker patching malicious controller firmware into a photovoltaic grid-connected inverter, thus mitigating the likelihood that the inverter becomes inactive a cyber-attack scenario. With this mitigation technique, if a cyberattack is successful and an attacker gains control of the network, a cyber-defense technique is in place to mitigate the impact of the cyber-attack. This additional protection layer was developed based on an innovative concept known as Digital Twin (DT). A DT, in this case, replicates an Active-Neutral Point Clamped (ANPC) inverter and was designed using a hardware language known as VHDL (Very High-Speed Integrated Circuit Hardware Description Language) and applied to Field-Programmable-GateArray (FPGA). The DT is embedded within the FPGA and contained in a controller board, the UCB (Unified Controller Board), developed by the University of Arkansas electrical engineering team. This UCB also contains two Digital Signal Processors (DSPs) responsible for generating associated signals to control an authentic physical inverter. These DSP signals are received and processed by the FPGA that implements the DT of an ANPC; in other words, it simulates in realtime the expected output of an actual ANPC inverter using the signals from the DSP. When a new firmware is ready to be patched, the DT provides output signals simulating behavior that a real ANPC inverter would generate with the new firmware. The new firmware is tested to check if it meets all the operational requirements established using a Design-For-Trust technique (DFTr). If the new firmware fails in at least one of the DFT tests, it is considered malicious and must be rejected. This work is divided into sections, such as Background, which explains the pieces that were used and the strategy behind this work; Process and Procedure, which explains the methodology that was adopted to prove the reliability and effectiveness of this work; Results and Discussion, where the simulations and results are described and explained; followed by Conclusion and Future work section, which concludes this work and adds possible future projects to continue this work further.
Large power electronics systems like multi-port autonomous reconfigurable solar power plant (MARS) are increasingly being researched upon to integrate emerging energy sources. MARS connects photovoltaic (PV) systems and energy storage systems (ESSs) to high-voltage direct current (HVdc) links/grids and high-voltage alternating current (ac) transmission grids. As these large power electronics systems incorporate complex hierarchical control systems that are close-by and communicate fast, the control systems require an unique power electronic hardware-in-the-loop (PE-HIL) real-time architecture to evaluate individual controllers. In this paper, a PE-HIL real-time architecture is proposed to evaluate one of the hundreds to thousands of digital signal processors (DSPs) that are a part of the complex hierarchical control system. The DSP connects to a central processing unit (CPU) and a field programmable gate array (FPGA) that form a part of the upper levels of the control system. The DSP is part of the lower level of the control system. The proposed PE-HIL architecture is tested and evaluated. Preliminary test results are presented to showcase the concept.