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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Power converter with co-packaged secondary field effect transistors (FETs)

A power converter with co-packaged secondary field effect transistors (FETs) are described. The power converter can include a first circuit, a transformer connected to an output of the first circuit, and a second circuit connected to an output of the transformer. The second circuit can include an inductor, a first FET coupled between the transformer and the inductor, and a second FET coupled between the first FET and ground. The first FET and the second FET can be co-packaged as a single package.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2020

Dielectrophoresis assisted rapid, selective and single cell detection of antibiotic resistant bacteria with G-FETs

Time-consuming, expensive and low sensitivity diagnostic methods used for monitoring bacterial infections lead to unnecessary or delays in prescription of the right antibiotic treatment. Determining an optimal clinical treatment requires rapid detection and identification of pathogenic bacteria and their sensitivity to specific antimicrobials. However, diagnostic devices that meet all of these criteria have proven elusive thus far. Graphene field effect transistors (G-FET) are a promising solution, since they are highly sensitive to chemical/biological modification, can have fast detection times and can be placed on different substrates. Here, by integrating specific peptide probes over G-FETs, we present a proof-of-concept study for species and strain specific label-free detection of clinical strains of pathogenic bacteria with high specificity and sensitivity. We found that pyrene-conjugated peptides immobilized on G-FETs were capable of detecting pathogenic Staphylococcus aureus at the single-cell level and discriminate against other gram-positive and gram-negative bacterial pathogens. A similar device was able to discriminate between antibiotic resistant and sensitive strains of Acinetobacter baumannii , suggesting that these devices can also be used for detecting antibiotic resistive pathogens. Furthermore, a new means of enhancing attachment, electric-field assisted binding, reduced the detection limit to 104 cells/ml and the detection time to below 5 minutes. Here, the combination of single step attachment, inexpensive production, rapid, selective and sensitive detection suggest G-FETs plus pyrene-conjugated peptides are a new platform for solving major challenges faced in point of care diagnostics to fight infectious diseases and antimicrobial resistance.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2020

Nano-FET-enabled biosensors: Materials perspective and recent advances in North America

Field-effect transistor (FET) is a very promising platform for biosensor applications due to its magnificent properties, including label-free detection, high sensitivity, fast response, real-time measurement capability, low running power, and the feasibility to miniaturize to a portable device. 1D (e.g. carbon nanotubes, Si nanowires, conductive polymer nanowires, 1D metal oxides, and others) and 2D (e.g. graphene materials, transition metal dichalcogenides, black phosphorus, and 2D metal oxides) materials, with their unique structural and electronic properties that are unavailable in bulk materials, have helped improve the sensitivity of FET biosensors and enabled detection down to single molecule. In this article, we give insights into the rapidly evolving field of 1D and 2D materials-based FET biosensors, with an emphasis on structure and electronic properties, synthesis, and biofunctionalization approaches of these nanomaterials. In addition, the progress in the 1D/2D-FET biosensors in North America, in the last decade, is summarized in tables. Moreover, challenges and future perspectives of 1D/2D-FET biosensors are covered.

1D materials↗
DOE OSTI2025

Extreme Enhancement-Mode Operation Accumulation Channel Hydrogen-Terminated Diamond FETs with V th < -6 V and High on-Current

In this work, a new Field Effect Transistor device concept based on hydrogen-terminated diamond (H-diamond) is demonstrated that operates in an Accumulation Channel rather than a Transfer Doping regime. The FET devices demonstrate both extreme enhancement-mode operation and high on-current with improved channel charge mobility compared to Transfer-Doped equivalents. Electron-beam evaporated Al 2 O 3 is used on H-diamond to suppress the Transfer Doping mechanism and produce an extremely high ungated channel resistance. A high-quality H-diamond surface with an unpinned Fermi level is crucially achieved, allowing for the formation of a high-density hole accumulation layer by gating the entire device channel which is encapsulated in dual-stacks of Al 2 O 3 . Completed devices with gate/channel length of 1 µm demonstrate record threshold voltage < -6 V with on-current > 80 mA mm -1 . Carrier density and mobility figures extracted by CV analysis indicate a high 2D charge density of ≈ 2 × 10 12 cm -2 and increased hole mobility of 110 cm 2 V -1 s -1 in comparison with more traditional Transfer-Doped H-diamond FETs. These results demonstrate the most negative threshold voltage yet reported for H-diamond FETs and highlight a powerful new strategy to greatly improve carrier mobility and enable enhanced high power and high frequency diamond transistor performance.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

Prediction of Alpha-Particle-Immune Gate-All-Around Field-Effect Transistors (GAA-FET) Based SRAM Design

Alpha particles are known to be a major source of particles creating soft errors in semiconductor devices, such as content flipping in Static Random-Access Memory (SRAM). Recent advancements in transistor nodes have led to the introduction of Gate-All-Around Field Effect Transistors (GAA-FETs), which have better gate control, thus better electrostatics. Moreover, the introduction of bottom dielectric isolation (BDI) eliminates substrate leakage and thus is expected to enhance its radiation hardness. It is thus important to explore if one can design an SRAM that is completely radiation-hard to alpha particles. In this paper, using 3D Technology Computer-Aided-Design (TCAD) simulations, we show that it is possible to design an SRAM using GAA-FET technology so that it is immune to single alpha particle radiation error. In other words, with the design, there will be no single-event upset (SEU) due to alpha particles. We first use ab initio calculations in PHITS to show that there is a maximum linear energy transfer (LET), LET max , for the alpha particle in Si and Si x Ge 1-x . Based on that, by de signing a sub-7nm GAA-FET-based SRAM with BDI, we show that the SRAM does not flip even if the particle strike is in the worst-case scenario for LET > LET max .

42 ENGINEERING↗
DOE OSTI2026

Multi-Objective Boundary Analysis of Discrete and Integrated SiC FET Modular Non-inverting Buck and Boost Converters for Fuel Cell EVs

This paper presents a multi-objective analysis of discrete and integrated SiC FET-based non-inverting buck-boost converter modules for modular fuel cell electric vehicle (EV) systems. Two converter ratings, 60 kW and 90 kW, are evaluated for both implementations, scalable up to 420 kW and 450 kW, respectively. Performance is assessed across efficiency, volumetric and gravimetric power density, cost, thermal stress, and estimated lifetime, where lifetime is derived from SiC FET B10 power-cycling data and junction temperature variations at rated power. A normalized overall performance index combined with a Pareto-boundary framework is used to identify configurations that optimally balance competing objectives. Results show that most configurations lie on the Pareto front, providing balanced trade-offs, while certain high-power discrete (90 kW at 450 kW) and integrated (60 kW at 180−420 kW) configurations are dominated. In general, discrete modules are more favorable for lower-power modular systems due to higher power density and lower cost, whereas integrated modules become more advantageous at higher power levels due to improved thermal behavior and longer lifetime. These findings provide practical design guidance for scalable fuel cell converter architectures and highlight the importance of system-level trade-offs in modular power electronics design.

Asa, Erdem [ORNL] (ORCID:0000000190884812)↗
DOE OSTI2026

Temperature-Dependent Transport Characteristics of 2D MoS2 Channel FETs Grown Using Salt-Based Precursors

D Transition Metal Dichalcogenides (TMDs), particularly MoS2, are promising candidates for sub-10 nm Gate All Around (GAA) CMOS FETs. Salt-assisted Chemical Vapor Deposition (CVD) enable lateral MoS2 growth at atmospheric pressure and low temperatures. This work analyzes salt-based precursor-driven CVD-grown MoS2 FETs at various temperatures. MoS2 was grown using Ammonium Molybdate salt, sulfurized at 750∘C, and transferred onto p−Si3/SiO2 substrates. At room temperature, threshold voltage (VT) ranged from -35 V to -25 V, with a peak drain current of 1.2μA/μm. As temperature increased above 325K, VT shifted exponentially, and carrier mobility dropped significantly. At 400 K, the gate lost channel control, though gate leakage current remained low. These results are compared with non-salt-based MoS2 growth to assess salt precursor effects.Notice: This manuscript has been authored by UT-Battelle, LLC, under contract DE-AC05-00OR22725 with the US Department of Energy (DOE). The US government retains and the publisher, by accepting the article for publication, acknowledges that the US government retains a nonexclusive, paid-up, irrevocable, worldwide license to publish or reproduce the published form of this manuscript, or allow others to do so, for US government purposes. DOE will provide public access to these results of federally sponsored research in accordance with the DOE Public Access Plan (https://www.energy.gov/doe-public-access-plan).

Jones, Andrew [ORNL] (ORCID:0009000233849687)↗
DOE OSTI2021

Optimized AC/DC Dual Active Bridge Converter using Monolithic SiC Bidirectional FET (BiDFET) for Solar PV Applications

Grid interface power conversion systems for commercial, industrial and residential solar power generation are becoming ubiquitous due to the competitive cost of solar energy. The AC/DC dual active bridge (DAB) converter is an upcoming topology in industrial PV energy and energy storage applications, providing bidirectional power transfer and galvanic isolation. In this paper, the properties of a DAB-type converter are leveraged to propose a design optimization process. It can optimize the high-frequency RMS current, size of magnetic elements and zero-voltage-switching (ZVS) region of the converter. The resulting design is compared against that derived from a conventional approach. In addition, an algorithm to compute the harmonic currents at the DC and line frequency AC ports of the system is proposed, and the respective filter designs are presented. The optimized design of the AC/DC DAB converter is implemented using the newly developed, 1200 V, 46 mΩ, four quadrant, SiC-based monolithic bidirectional FETs (BiDFET). Experimental results from the 2.3 kW, 400V/277VRMS hardware prototype are finally presented to verify the design process.

Bidirectional isolated AC-DC conversion, solar ene↗
DOE OSTI2024

FET Junction Temperature Monitoring Using Novel On-Chip Solution

A novel junction temperature monitoring sensor is proposed and experimentally demonstrated for application in MOS-gate power devices. The sensor is created using the polycide gate electrode layer of the devices to create a temperature-sensitive resistor without any additional fabrication steps. The resistor is located on the field oxide with one end grounded at the device reference terminal to isolate it from the device current and voltage transients. It allows in-situ monitoring of the device junction temperature during active circuit operation. The technology has been implemented to monitor the junction temperature of Silicon Carbide Junction Barrier Schottky Field Effect Transistors (SiC JBSFETs) with the bi-directional FET (BiDFET).

Bidirectional switches, SiC bidirectional FET, BiD↗
DOE OSTI2024

Variation Tolerant and Energy-Efficient Charge Domain Compute-in-Memory Array with Binary and Multi-Level Cell Ferroelectric FET

Here, in this work, we present a variation-tolerant and energy-efficient charge-domain Ferroelectric FET (FeFET) based Compute-in-Memory (CiM) array design that is compatible with both binary and multi-level cell memory sensing. We demonstrate that: 1) by exploiting FeFET as a nonvolatile switch, its high ON/OFF ratio in the subthreshold region can suppress the error introduced by the inaccurate ON state conductance, thus realizing robust CiM operations, unlike the current-domain CiM design where the computation results is highly sensitive to the device conductance variation; 2) by leveraging a dense dynamic random access memory (DRAM)-like 1FeFET1C cell structure, the proposed design benefits from the existing high density DRAM establishment while also significantly relaxing the capacitor retention and transistor leakage requirement; 3) the charge-domain CiM supports both binary FeFET with minimum overhead and MLC FeFET with tolerable latency for MLC state sensing, whose efficacy is validated experimentally on both cell-level and array-level; 4) the proposed CiM shows much better device variation resilience than conventional current-domain CiM, and also improves inference accuracy. Macro-level evaluation results demonstrate significantly higher energy efficiency and area efficiency compared to prior CiM works.

Duan, Jiahui [University of Notre Dame, IN (United↗
DOE OSTI2024

On the Origin of Holes During Polarization Reset in Floating Body Ferroelectric FETs Towards Improving Switching Efficiency

In this article, we performed a comprehensive combined experimental and modeling study on the polarization reset mechanisms of floating body (i.e., channel) ferroelectric FETs, an important class of device with growing interests due to added functionalities and improved reliabilities. Using fully-depleted silicon-on-insulator (FDSOI) FeFET as a classical example, we demonstrate that: 1) without hole generation mechanisms, floating body FeFETs during reset is simply a capacitor divider, with negligible ferroelectric voltage drop for switching; ii) Band-to-band-tunneling (BTBT) around gate-to-S/D overlap even with zero drain bias generates holes to facilitate the reset in FDSOI FeFET, though at a slower speed and hold the reset state; iii) With scaling, S/D inner fringe field can enable fast reset, thus offering a potential efficiency boost approach; iv) a compact FDSOI FeFET model is developed that can capture the BTBT effect and reproduce the observed behaviors; v) the reset mechanism is also validated in a NAND string composed of FDSOI FeFETs, demonstrating its relevant applications. These insights show the strategies in improving reset efficiency, i.e., enhanced BTBT and inner fringe field.

42 ENGINEERING↗
DOE OSTI2020

Tunnel-FET Switching Is Governed by Non-Lorentzian Spectral Line Shape

In tunnel field-effect transistors (tFETs), the preferred mechanism for switching occurs by alignment (on) or misalignment (off) of two energy levels or band edges. Unfortunately, energy levels are never perfectly sharp. When a quantum dot interacts with a wire, its energy is broadened. Its actual spectral shape controls the current/voltage response of such transistor switches, from on (aligned) to off (misaligned). The most common model of spectral line shape is the Lorentzian, which falls off as reciprocal energy offset squared. Unfortunately, this is too slow a turnoff, algebraically, to be useful as a transistor switch. Electronic switches generally demand an on/off ratio of at least a million. Steep exponentially falling spectral tails would be needed for rapid off-state switching. This requires a new electronic feature, not previously recognized: narrowband, heavy-effective mass, quantum wire electrical contacts, to the tunneling quantum states. These are a necessity for spectrally sharp switching.

42 ENGINEERING↗
DOE OSTI2023

Embedding security into ferroelectric FET array via in situ memory operation

Non-volatile memories (NVMs) have the potential to reshape next-generation memory systems because of their promising properties of near-zero leakage power consumption, high density and non-volatility. However, NVMs also face critical security threats that exploit the non-volatile property. Compared to volatile memory, the capability of retaining data even after power down makes NVM more vulnerable. Existing solutions to address the security issues of NVMs are mainly based on Advanced Encryption Standard (AES), which incurs significant performance and power overhead. In this paper, we propose a lightweight memory encryption/decryption scheme by exploiting in-situ memory operations with negligible overhead. To validate the feasibility of the encryption/decryption scheme, device-level and array-level experiments are performed using ferroelectric field effect transistor (FeFET) as an example NVM without loss of generality. Besides, a comprehensive evaluation is performed on a 128 × 128 FeFET AND-type memory array in terms of area, latency, power and throughput. Compared with the AES-based scheme, our scheme shows ~22.6×/~14.1× increase in encryption/decryption throughput with negligible power penalty. Furthermore, we evaluate the performance of our scheme over the AES-based scheme when deploying different neural network workloads. Our scheme yields significant latency reduction by 90% on average for encryption and decryption processes.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

Next-generation tunnel FETs: exploring material perspectives and areal tunneling configurations

The end of Dennard scaling, which facilitated proportional increases in computing power without added energy costs until the mid-2000s, has underscored the urgent need for innovative semiconductor devices that can enhance energy efficiency. Tunnel field-effect transistors (TFETs) have emerged as promising candidates to surpass the energy efficiency of conventional metal oxide semiconductor field-effect transistors (MOSFETs). Unlike MOSFETs, which rely on thermionic emission to overcome the source-channel potential barrier, TFETs operate through quantum tunneling, potentially enabling sub-60 mV dec −1 subthreshold swing (SS) for low-voltage operation. However, lateral TFETs have faced challenges in achieving adequate on-state current (I ON ) and a broad SS operation window, limiting their practical utility. This review article advocates for areal TFETs, which utilize face-to-face tunnel junctions that ideally offer step-function current turn-on characteristics and allow I ON to scale with device area rather than width. We highlight recent advancements in integrating 2D materials into tunneling structures, which could facilitate efficient band-to-band tunneling through atomically thin layers, while addressing challenges of gate field screening. We then discuss the nearer-term prospects of epitaxial areal TFETs comprising III–V compound semiconductors and group-IV semiconductors based on recent experimental progress. The review examines both quantum mechanical and semiclassical modeling approaches for TFETs, including techniques to reduce the computational complexity. The article delves into ongoing challenges in material synthesis, interface engineering, device fabrication, and integration pathways, concluding with recommendations for future research directions to overcome the fundamental power density limitations of conventional transistor technology.

2D materials↗
DOE OSTI2021

Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on the Device Variation of Ferroelectric FET

In this work, a comprehensive study of random spatial fluctuation of the ferroelectric (FE) phase and dielectric (DE) phase in FeFETs is conducted to understand its impact on device variation. It is found that: i) there exists a certain DE percentage threshold that below which the increase of the DE phase does not significantly impact the device memory window and variation and only above which evident device degradation can be observed; ii) increasing the DE phase increases the variation in the memory window and the coercive field distribution further exacerbates the variation, hence degrading the sensing margin; iii) decreasing the number of grains degrades the device variation, which calls for further grain size engineering for variation suppression.

42 ENGINEERING↗
DOE OSTI2022

On the Feasibility of 1T Ferroelectric FET Memory Array

To fully exploit the ferroelectric field effect transistor (FeFET) as compact embedded nonvolatile memory for various computing and storage applications, it is desirable to use a single FeFET (1T) as a unit cell and arrange the cells into an array. However, many write mechanisms for an 1T FeFET array reported in the literature are yet to be validated experimentally. In this work, we performed a comprehensive experimental characterization on the write operations in an 1T- NOR and 1T- AND array using n-channel bulk FeFETs. We discovered that: 1) the source/drain contact can only supply minority carriers (i.e., electrons) to the channel for polarization screening during the low- V TH state programming; 2) the body contact can not only supply majority carriers (i.e., holes) for efficient high- V TH state write, but also depletion charge for low- V TH state programming, though with lower efficiency; and 3) during the low/high- V TH programming, only the path that can supply negative/positive screening charges, respectively, need to respond, which necessitates the application of proper write biases on the corresponding terminal. Based on the understanding of these write mechanisms, we show the importance of localized body contact or column-wise body contact for the successful high- V TH state programming. We also show that the previously proposed C- AND write scheme fails to program the FeFET to the low- V TH state for our devices. Finally, we propose several write schemes for both 1T- AND and 1T- NOR arrays for various scenarios providing insights for choosing the appropriate write scheme, which will facilitate the adoption of 1T FeFET memory arrays for emerging applications.

FeFET↗