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Results for “Field Programmable Gate Array (FPGA)”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2017

Digitization of Analog Signals using a Field Programmable Gate Array (FPGA)

The idea of this research is consolidating the electrical components used for capturing data in the Mu2e Tracker. Ideally, an FPGA will serve as the Time-Division Converters (TDC) and Analog-to-Digital Converters (ADC). The TDC is already being carried out by the FPGA, but we are still using off the shelf ADCs. This poster proposes using Low Voltage Differential Signaling as the basis for analog-to-digital conversion using and FPGA.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

FPGA Computing

The articles in this special section focus on cutting-edge research on topics that relate to field programmable gate arrays (FPGA) in computing.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

An 8.8 ps RMS Resolution Time-To-Digital Converter Implemented in a 60 nm FPGA with Real-Time Temperature Correction

This paper presented a non-uniform multiphase (NUMP) time-to-digital converter (TDC) implemented in a field-programmable gate array (FPGA) with real-time automatic temperature compensation. NUMP-TDC is a novel, low-cost, high-performance TDC that has achieved an excellent performance in Altera Cyclone V FPGA. The root mean square (RMS) for the intrinsic timing resolution was 2.3 ps. However, the propagation delays in the delay chain of some FPGAs (for example, the Altera Cyclone 10 LP) vary significantly as the temperature changes. Thus, the timing performances of NUMP-TDCs implemented in those FPGAs are significantly impacted by temperature fluctuations. In this study, a simple method was developed to monitor variations in propagation delays using two registers deployed at both ends of the delay chain and compensate for changes in propagation delay using a look-up table (LUT). When the variations exceeded a certain threshold, the LUT for the delay correction was updated, and a bin-by-bin correction was launched. Using this correction approach, a resolution of 8.8 ps RMS over a wide temperature range (5 °C to 80 °C) had been achieved in a NUMP-TDC implemented in a Cyclone 10 LP FPGA.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2023

ESnet/JLab FPGA Accelerated Transport

To increase the science rate for high data rates/volumes, Thomas Jefferson National Accelerator Facility (JLab) has partnered with Energy Sciences Network (ESnet) to define an edge to data center traffic shaping / steering transport capability featuring data event aware network shaping and forwarding. The keystone of this ESnet+JLab FPGA Accelerated Transport (EJFAT) is the joint development of an AI/ML directed dynamic compute work Load Balancer (LB) of UDP streamed data. The LB is a suite consisting of a Field Programmable Gate Array (FPGA) executing the dynamically configurable, low fixed latency LB data plane featuring real-time packet redirection and high throughput, and a control plane running on the FPGA host computer that monitors network and compute farm telemetry in order to make dynamic AI/ML guided decisions for destination compute host redirection/load balancing and destination resource provisioning. The LB provides for three-tier horizontal scaling across LB suites, core compute hosts, and CPUs within a host. The LB effectively provides seamless integration of edge/core computing to support direct experimental data processing for immediate use by JLab science programs and others such as the EIC as well as data centers of the future requiring high throughput and low latency for both hot and cooled data for both running experiment data acquisition systems and data center use cases.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2014

Design, Implementation, and Evaluation of a Hybrid DS/FFH Spread-Spectrum Radio Transceiver

In recent years there has been great interest in using hybrid spread-spectrum (HSS) techniques for commercial applications, particularly in the Smart Grid, in addition to their inherent uses in military communications. This is because HSS can accommodate high data rates with high link integrity, even in the presence of significant multipath effects and interfering signals. A highly useful form of this transmission technique for many types of command, control, and sensing applications is the specific code-related combination of standard direct-sequence modulation with "fast" frequency-hopping, denoted hybrid DS/FFH, wherein multiple frequency hops occur within a single data-bit time. In this paper, we present the efforts carried out at Oak Ridge National Laboratory toward exploring the design, implementation, and evaluation of a hardware prototypic hybrid DS/FFH spread-spectrum radio transceiver using a single Field Programmable Gate Array (FPGA). The high integration within a single FPGA allows the various subsystems to easily communicate with each other and thereby maintain tight synchronization. We investigate various hopping sequences against robustness to interference and jamming. Experimental results are presented to show the receiver sensitivity, radio data rate evaluation, and jamming-rejection capability of the implemented hybrid DS/FFH spread-spectrum system under widely varying design parameters.

direct-sequence↗
DOE OSTI2018

Fast inference of deep neural networks in FPGAs for particle physics

Here, recent results at the Large Hadron Collider (LHC) have pointed to enhanced physics capabilities through the improvement of the real-time event processing techniques. Machine learning methods are ubiquitous and have proven to be very powerful in LHC physics, and particle physics as a whole. However, exploration of the use of such techniques in low-latency, low-power FPGA (Field Programmable Gate Array) hardware has only just begun. FPGA-based trigger and data acquisition systems have extremely low, sub-microsecond latency requirements that are unique to particle physics. We present a case study for neural network inference in FPGAs focusing on a classifier for jet substructure which would enable, among many other physics scenarios, searches for new dark sector particles and novel measurements of the Higgs boson. While we focus on a specific example, the lessons are far-reaching. A companion compiler package for this work is developed based on High-Level Synthesis (HLS) called hls4ml to build machine learning models in FPGAs. The use of HLS increases accessibility across a broad user community and allows for a drastic decrease in firmware development time. We map out FPGA resource usage and latency versus neural network hyperparameters to identify the problems in particle physics that would benefit from performing neural network inference with FPGAs. For our example jet substructure model, we fit well within the available resources of modern FPGAs with a latency on the scale of 100 ns.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Ferroelectric FET-based context-switching FPGA enabling dynamic reconfiguration for adaptive deep learning machines

Field programmable gate array (FPGA) is widely used in the acceleration of deep learning applications because of its reconfigurability, flexibility, and fast time-to-market. However, conventional FPGA suffers from the trade-off between chip area and reconfiguration latency, making efficient FPGA accelerations that require switching between multiple configurations still elusive. Here, we propose a ferroelectric field-effect transistor (FeFET)–based context-switching FPGA supporting dynamic reconfiguration to break this trade-off, enabling loading of arbitrary configuration without interrupting the active configuration execution. Leveraging the intrinsic structure and nonvolatility of FeFETs, compact FPGA primitives are proposed and experimentally verified. The evaluation results show our design shows a 63.0%/74.7% reduction in a look-up table (LUT)/connection block (CB) area and 82.7%/53.6% reduction in CB/switch box power consumption with a minimal penalty in the critical path delay (9.6%). Besides, our design yields significant time savings by 78.7 and 20.3% on average for context-switching and dynamic reconfiguration applications, respectively.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

High performance context switching for virtualized FPGA accelerators

A hardware context manager in a field-programmable gate array (FPGA) device includes configuration logic configured to program one or more programming regions in the FPGA device based on configuration data for implementing a target configuration of the one or more programming regions. Context management logic in the hardware context manager is coupled with the configuration logic and saves a first context corresponding to the target configuration by retrieving first state information from the set of one or more programming regions, where the first state information is generated based on the target configuration, and storing the retrieved first state information in a context memory. The context management logic restores the first context by transferring the first state information from the context memory to the one or more programming regions, and causing the configuration logic to program the one or more programming regions based on the configuration data.

42 ENGINEERING↗
DOE OSTI2018

FPGA based demodulation of laser induced fluorescence in plasmas

We present a field programmable gate array (FPGA)-based system that counts photons from laser-induced fluorescence (LIF) on a laboratory plasma. This is accomplished with FPGA-based up/down counters that demodulate the data, giving a background-subtracted LIF signal stream that is updated with a new point as each laser amplitude modulation cycle completes. We demonstrate using the FPGA to modulate a laser at 1 MHz and demodulate the resulting LIF data stream. Finally, this data stream is used to calculate an LIF-based measurement sampled at 1 MHz of a plasma ion fluctuation spectrum.

47 OTHER INSTRUMENTATION↗
DOE OSTI2016

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2019

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

42 ENGINEERING↗
DOE OSTI2021

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

Asaad, Sameh W.↗
DOE OSTI2021

Architecture Of A Multi-channel Data Streaming Device With An Fpga As A Coprocessor

The design of a data acquisition system often involves the integration of a Field Programmable Gate Array (FPGA) with analog front-end components to achieve precise timing and control. Reuse of these hardware systems can be difficult since they need to be tightly coupled to the communications interface and timing requirements of the specific ADC used. A hybrid design exploring the use of FPGA as a coprocessor to a traditional CPU in a dataflow architecture is presented. Reduction in the volume of data and gradual transitioning of data processing away from a hard real-time environment are both discussed. Chief design concerns, including data throughput and precise synchronization with external stimuli, are addressed. The discussion is illustrated by the implementation of a multi-channel digital integrator, a device based entirely on commercial off-the-shelf (COTS) equipment.

Nogiec, Jerzy M.↗
DOE OSTI2014

Digitalized two parametric system for gamma/neutron spectrometry - Paper 59

Many types of detectors like stilbene, NE-213 etc. in conjunction with photomultiplier loaded with low working resistance produce pulses of approximately 100 ns length and contain information about deposited particle in the trailing edge. Using fast analog to digital converters (ADC) and field-programmable gate array (FPGA) it is possible to create a spectrometric system working in mixed gamma and neutron fields which is not loaded dead time. The count rate of processed pulses can reach more than one million per second. Such a high count rate of processed pulses can be achieved due to the pulse processing is implemented in FPGA. The output of this pulse processing is amplitude which describes the energy of deposited particle and discrimination parameter whereby it is possible to discriminate photons and neutrons. To increase the dynamic range of energy of detectable particle the signal from photomultiplier is separated into two branches with different amplification. Each branch is digitalized by separate ADC. Components from which the system is composed are so light that the spectrometer can be easily transported. Its weight is less than 3 kilograms. Spectrometer was tested in the research reactor LR-0 in Rez near Prague (Czech Republic). The measured data was processed using deconvolution into a neutron flux density and compared with nowadays used analog spectrometer and simulation result. Measured neutron spectrum of Cf-252 is included. (authors)

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2017

Mitigated FPGA design of multi-gigabit transceivers for application in high radiation environments of High Energy Physics experiments

SRAM-ba8ed Field Programmable Gate Array (FPGA) logic devices arc very attractive in applications where high data throughput is needed, such as the latest generation of High Energy Physics (HEP) experiments. FPGAs have been rarely used in such experiments because of their sensitivity to radiation. The present paper proposes a mitigation approach applied to commercial FPGA devices to meet the reliability requirements for the front-end electronics of the Liquid Argon (LAr) electromagnetic calorimeter of the ATLAS experiment, located at CERN. Particular attention will be devoted to define a proper mitigation scheme of the multi-gigabit transceivers embedded in the FPGA, which is a critical part of the LAr data acquisition chain. A demonstrator board is being developed to validate the proposed methodology. :!\litigation techniques such as Triple Modular Redundancy (T:t\IR) and scrubbing will be used to increase the robustness of the design and to maximize the fault tolerance from Single-Event Upsets (SEUs).

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2018

Pulse discrimination with a Gaussian mixture model on an FPGA

A Gaussian Mixture Model (GMM) based machine learning algorithm has been applied to the problem of gamma/neutron pulse shape discrimination (PSD). The algorithm has been successfully implemented on a standard PC as well as a field programmable gate array (FPGA). We describe the GMM classifier and its implementation on these two different types of hardware. We compare the performance of the algorithm on these two platforms against each other, along with other standard techniques applied in PSD. Our results show that the FPGA-based GMM classifier outperforms the standard PSD techniques in terms of classification accuracy at low particle energy and executes more quickly than its CPU-based counterpart.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2019

The JET upgraded toroidal Alfvén Eigenmode Diagnostic System

The Alfvén Eigenmode Active Diagnostic system (AEAD) has undergone a major upgrade and redesign to provide a state-of-the-art excitation and real-time detection system for JET. The new system consists of individual 4 kW amplifiers allowing for increased current, separate excitation and real time control of relative phasing between antenna currents. The amplifiers have a frequency range of 10–1000 kHz, divided into various frequency bands by external matching filters. Due to the varying transmission line impedance throughout the frequency range, the amplifiers were designed with a very high resilience to reflected power. The existing amplifier control electronics have been replaced with a digital control system incorporating a National Instruments platform and Field Programmable Gate Array (FPGA) modules for frequency, gain and phase control with a frequency and phase resolution of less than 1 kHz and 1 degree respectively. Complementing the digital control system is the Protection and Control System, which utilizes Field Programmable Analog Arrays (FPAAs) and an array of electronic devices to monitor and control the AEAD. New capabilities such as independent antenna current/phase control, allow for improved excitation control, better definition of antenna spectrum combined with enhanced system reliability. This paper will review the new AEAD system, its unique capabilities and improvements over the previous diagnostic system.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2017

SRF Cavity Testing Using a FPGA Self Excited Loop

This document provides a detailed description of procedures for very-high precision calibration and testing of superconducting RF cavities using digital Low-Level RF (LLRF) electronics based on Field Programmable Gate Arrays (FPGA). The use of a Self-Excited Loop with an innovative procedure for fast turn-on allows the measurement of the forward, reflected and transmitted power from a single port of the directional coupler in front of the cavity, thus eliminating certain measurement errors. Various procedures for measuring the quality factor as a function of cavity fields are described, including a single RF pulse technique. Errors are estimated for the measurements.

43 PARTICLE ACCELERATORS↗