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At least 19 records

Superconducting qubits in a flip-chip architecture

Flip-chip architectures have recently enabled significant scaling-up of multi-qubit circuits and have been used to assemble hybrid quantum systems that combine different substrates, for example, for quantum acoustics experiments. The standard flip-chip method uses superconducting galvanic connections between two substrates, typically implemented using sophisticated indium wafer-bonding systems, which give highly reliable and temperature-cyclable assemblies, but are expensive, somewhat inflexible in design, and require robust substrates that can sustain the large compressive forces required to cold-weld the indium bonds. A much simpler method is to assemble dies using very low-force contacts and air-dried adhesives, although this does not provide a galvanic contact between the dies. In this work, we demonstrate that the latter technique can be used to reliably couple superconducting qubit circuits, in which the qubits are on separate dies, without the need for a galvanic connection. We demonstrate full vector qubit control of each qubit on each of the two dies, with high-fidelity single-shot readout, and further demonstrate entanglement-generating excitation swaps as well as benchmark a controlled-Z entangling gate between the two qubits on the two dies. This exemplifies a simple and inexpensive assembly method for two-plus-one-dimensional quantum circuit integration that supports the use of delicate or unusually shaped substrates.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Optimization of Indium Bump Morphology for Improved Flip Chip Devices

Flip-chip hybridization, also known as bump bonding, is a packaging technique for microelectronic devices that directly connects an active element or detector to a substrate readout face-to-face, eliminating the need for wire bonding. In order to make conductive links between the two parts, a solder material is used between the bond pads on each side. Solder bumps, composed of indium metal, are typically deposited by thermal evaporation onto the active regions of the device and substrate. While indium bump technology has been a part of the electronic interconnect process field for many years and has been extensively employed in the infrared imager industry, obtaining a reliable, high-yield process for high-density patterns of bumps can be quite difficult. Under the right conditions, a moderate hydrogen plasma exposure can raise the temperature of the indium bump to the point where it can flow. This flow can result in a desirable shape where indium will efficiently wet the metal contact pad to provide good electrical contact to the underlying readout or imager circuit. However, it is extremely important to carefully control this process as the intensity of the hydrogen plasma treatment dramatically affects the indium bump morphology. To ensure the fine-tuning of this reflow process, it is necessary to have realtime feedback on the status of the bumps. With an appropriately placed viewport in a plasma chamber, one can image a small field (a square of approximately 5 millimeters on each side) of the bumps (10-20 microns in size) during the hydrogen plasma reflow process. By monitoring the shape of the bumps in real time using a video camera mounted to a telescoping 12 magnifying zoom lens and associated optical elements, an engineer can precisely determine when the reflow of the bumps has occurred, and can shut off the plasma before evaporation or de-wetting takes place.

Jones, Todd J.↗

Advanced Flip Chips in Extreme Temperature Environments

The use of underfill materials is necessary with flip-chip interconnect technology to redistribute stresses due to mismatching coefficients of thermal expansion (CTEs) between dissimilar materials in the overall assembly. Underfills are formulated using organic polymers and possibly inorganic filler materials. There are a few ways to apply the underfills with flip-chip technology. Traditional capillary-flow underfill materials now possess high flow speed and reduced time to cure, but they still require additional processing steps beyond the typical surface-mount technology (SMT) assembly process. Studies were conducted using underfills in a temperature range of -190 to 85 C, which resulted in an increase of reliability by one to two orders of magnitude. Thermal shock of the flip-chip test articles was designed to induce failures at the interconnect sites (-40 to 100 C). The study on the reliability of flip chips using underfills in the extreme temperature region is of significant value for space applications. This technology is considered as an enabling technology for future space missions. Flip-chip interconnect technology is an advanced electrical interconnection approach where the silicon die or chip is electrically connected, face down, to the substrate by reflowing solder bumps on area-array metallized terminals on the die to matching footprints of solder-wettable pads on the chosen substrate. This advanced flip-chip interconnect technology will significantly improve the performance of high-speed systems, productivity enhancement over manual wire bonding, self-alignment during die joining, low lead inductances, and reduced need for attachment of precious metals. The use of commercially developed no-flow fluxing underfills provides a means of reducing the processing steps employed in the traditional capillary flow methods to enhance SMT compatibility. Reliability of flip chips may be significantly increased by matching/tailoring the CTEs of the substrate material and the silicon die or chip, and also the underfill materials. Advanced packaging interconnects technology such as flip-chip interconnect test boards have been subjected to various extreme temperature ranges that cover military specifications and extreme Mars and asteroid environments. The eventual goal of each process step and the entire process is to produce components with 100 percent interconnect and satisfy the reliability requirements. Underfill materials, in general, may possibly meet demanding end use requirements such as low warpage, low stress, fine pitch, high reliability, and high adhesion.

Ramesham, Rajeshuni↗

Organic flip chip reliability study for space applications

The current state-of-the-art flip chip packages for space applications are the class-Y non-hermetic ceramic packages, whereas for commercial applications, organic packages have been the mainstream technology for about two decades. The high reliability of the class-Y parts suggests that the hermeticity is not critical for the reliability of flip chip devices and that organic flip chip packages could be reliable enough for space applications. The current report summarizes the result of collaboration between JPL and Cobham semiconductor space solutions to study the reliability of the organic flip chip packages.

Measmer, Rich↗

AE (Acoustic Emission) for Flip-Chip CGA/FCBGA Defect Detection

C-mode scanning acoustic microscopy (C-SAM) is a nondestructive inspection technique that uses ultrasound to show the internal feature of a specimen. A very high or ultra-high-frequency ultrasound passes through a specimen to produce a visible acoustic microimage (AMI) of its inner features. As ultrasound travels into a specimen, the wave is absorbed, scattered or reflected. The response is highly sensitive to the elastic properties of the materials and is especially sensitive to air gaps. This specific characteristic makes AMI the preferred method for finding "air gaps" such as delamination, cracks, voids, and porosity. C-SAM analysis, which is a type of AMI, was widely used in the past for evaluation of plastic microelectronic circuits, especially for detecting delamination of direct die bonding. With the introduction of the flip-chip die attachment in a package; its use has been expanded to nondestructive characterization of the flip-chip solder bumps and underfill. Figure 1.1 compares visual and C-SAM inspection approaches for defect detection, especially for solder joint interconnections and hidden defects. C-SAM is specifically useful for package features like internal cracks and delamination. C-SAM not only allows for the visualization of the interior features, it has the ability to produce images on layer-by-layer basis. Visual inspection; however, is only superior to C-SAM for the exposed features including solder dewetting, microcracks, and contamination. Ideally, a combination of various inspection techniques - visual, optical and SEM microscopy, C-SAM, and X-ray - need to be performed in order to assure quality at part, package, and system levels. This reports presents evaluations performed on various advanced packages/assemblies, especially the flip-chip die version of ball grid array/column grid array (BGA/CGA) using C-SAM equipment. Both external and internal equipment was used for evaluation. The outside facility provided images of the key features that could be detected using the most advanced C-SAM equipment with a skilled operator. Investigation continued using in-house equipment with its limitations. For comparison, representative X-rays of the assemblies were also gathered to show key defect detection features of these non-destructive techniques. Key images gathered and compared are: Compared the images of 2D X-ray and C-SAM for a plastic LGA assembly showing features that could be detected by either NDE technique. For this specific case, X-ray was a clear winner. Evaluated flip-chip CGA and FCBGA assemblies with and without heat sink by C-SAM. Only the FCCGA package that had no heat sink could be fully analyzed for underfill and bump quality. Cross-sectional microscopy did not revealed peripheral delamination features detected by C-SAM. Analyzed a number of fine pitch PBGA assemblies by C-SAM. Even though the internal features of the package assemblies could be detected, C-SAM was unable to detect solder joint failure at either the package or board level. Twenty times touch ups by solder iron with 700degF tip temperature, each with about 5 second duration, did not induce defects to be detected by C-SAM images. Other techniques need to be considered to induce known defects for characterization. Given NASA's emphasis on the use of microelectronic packages and assemblies and quality assurance on workmanship defect detection, understanding key features of various inspection systems that detect defects in the early stages of package and assembly is critical to developing approaches that will minimize future failures. Additional specific, tailored non-destructive inspection approaches could enable low-risk insertion of these advanced electronic packages having hidden and fine features.

Ghaffarian, Reza↗

Study of bonding methods for flip chip and beam leaded devices

The results are presented of a comprehensive study and evaluation for the bonding of flip chip and beam leaded devices onto hybrid microcircuit substrates used in high reliability space applications. The program included the evaluation of aluminum flip chips, solder (silver/tin) bump chips, gold beam leaded devices, and aluminum beam leaded devices.

Rudd, H. C.↗

On-PIC Light Source Integration & Micro-dispensing of Solder Paste for Flip Chip Application

To reach the next level benefits of photonic integrated circuits (PICs), the Integrated Photonic Systems Roadmap-International describes the necessity of either heterogeneous or hybrid integration of light sources [1]. A new approach for hybrid integration is Photonic Wire Bonding where 3D nanolithography is used to pattern a polymer waveguide that connects light sources to PIC waveguides. The waveguides resemble electrical wire bonds and essentially do the same as their electrical counterpart for packaging photonic chips together. In order to reap the full benefits of a photonic wire bonds, the light source must be carefully packaged. In this work I seek to expand RIT’s photonic packaging capability by establishing a packaging process to integrate light sources, specifically an Indium Phosphide distributed feedback lasers and a reflective semiconductor optical amplifiers, directly onto a photonic integrated circuits. Another necessary requirement for PIC packaging is densely integrated electrical connectivity. In this thesis I developed a fine pitch flip chip interconnect technique demonstrated using gold stud bumps in conjunction with micro-dispensed solder paste. This work opens the door to high density photonic flip chip applications. The micro-dispensed solder paste dots having diameters 50-125 µm are currently being tested at a pitch of 150 µm . The gold stud bumps are formed with 1mil gold wire creating bumps with a diameter of 40-60 µm depending on specific parameter values. These capabilities will allow RIT to assemble and test novel photonic integrated devices, cutting down on the time and cost associated with third party assembly and tests facilities. Thereby keeping RIT at the forefront of photonic research.

Wongk, Nicole↗

A 90 GHz Amplifier Assembled Using Flip-Chip Technology

This letter reports the performance of a novel single-stage W-band amplifier fabricated utilizing flip-chip bump-bonding. We have bump-bonded a high-speed, low-noise InP high electron mobility transistor (HEMT) device onto a separately fabricated passive circuit having a GaAs substrate.

FET amplifiers Millimeter wave FETs bump-bonding m↗

Preliminary reliability evaluation of flip chip on flex interconnect technology

The study was carried out to evaluate the flip-chip-on-flex (FCOF) interconnection process in order to determine its feasibility for space flight applications. The key objectives were to: develop and apply simple and cost effective process steps needed to manufacture FCOFs and build test samples; perform a preliminary technology validation, and determine any initial environmental or application risks. The FCOF was shown to be simpler and more economical than other chip interconnection schemes.

Shaw, Jack J.↗

Flip-Chip Carrier Would Match Microwave FET Impedances

Proposed field-effect transistor consists of three cells which make up one complete FET pellet. Pellet is flip-chip mounted on carrier with source grounded gate and drain posts connected directly to impedance-matching transmission-line segments. Impedance transformers are part of mounting and contact strips.

Huang, H. C.↗

Photonic integration of Er 3+ :Y 2 SiO 5 with thin-film lithium niobate by flip chip bonding

Rare earth ions are known as promising candidates for building quantum light-matter interface. However, tunable photonic cavity access to rare earth ions in their desired host crystal remains challenging. Here, we demonstrate the integration of erbium doped yttrium orthosilicate (Er 3+ :Y 2 SiO 5 ) with thin-film lithium niobate photonic circuit by plasma-activated direct flip chip bonding. Resonant coupling to erbium ions is realized by on-chip electro-optically tuned high Q lithium niobate micro-ring resonators. Fluorescence and absorption of erbium ions at 1536.48 nm are measured in the waveguides, while the collective ion-cavity cooperativity with micro-ring resonators is assessed to be 0.36. This work presents a versatile scheme for future rare earth ion integrated quantum devices.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Flip chip packaging of a MEMS neuro-prosthetic system

A joint research team from California Institute of Technology and Jet Propulsion Laboratory is developing a fully miniaturized, smart implantable neuro-prosthetic system, by combining integrated electronics with Micro Electro Mechanical Structure (MEMS) based electrode arrays. The packaging group of this project team has been tasked with designing and fabricating a package to interface electrically between a MEMS electrode array, capable of extracting signals from brain, and an electronic chip, capable of providing on chip conditioning/processing of extracted data, while delivering the output data to a detector located outside the body.

flip↗

Physics of Failure Analysis of Xilinx Flip Chip CCGA Packages: Effects of Mission Environments on Properties of LP2 Underfill and ATI Lid Adhesive Materials

The Xilinx Virtex 4QV and 5QV (V4 and V5) are next-generation field-programmable gate arrays (FPGAs) for space applications. However, there have been concerns within the space community regarding the non-hermeticity of V4/V5 packages; polymeric materials such as the underfill and lid adhesive will be directly exposed to the space environment. In this study, reliability concerns associated with the non-hermeticity of V4/V5 packages were investigated by studying properties and behavior of the underfill and the lid adhesvie materials used in V4/V5 packages.

Suh, Jong-ook↗