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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1985

On instruction sets and their formats

Central to instruction set design is the issue of the instruction format. Some common format encoding techniques are discussed, and a method of representing high-level language parse trees by means of formats that cover successively larger portions of a tree is introduced. Variations are introduced on the method that represent directed acyclic graphs as well as simple parse trees, and that encode constants in a special fashion. For a particular representation, the number of times each format is executed to run a sample program to completion is measured.

Flynn, M. J.↗
DOE OSTI2026

Hybrid Oscillator-Qubit Quantum Processors: Instruction Set Architectures, Abstract Machine Models, and Applications

This tutorial offers a pedagogical guide to hybrid quantum processors that integrate discrete-variable (DV) qubits and continuous-variable (CV) oscillators. Aimed at computer scientists, engineers, and physicists, it provides an overview of the experimental, algorithmic, and architectural aspects of this novel and rapidly developing hardware model. Experimental realizations of this model include superconducting, trapped-ion, and neutral-atom platforms. By combining DV and CV components, hybrid oscillator-qubit processors enable a powerful new paradigm that offers complementary strengths for quantum control, error correction, computation, and simulation. Working toward the goal of a full-stack system connecting applications to CV-DV hardware, we define and formulate abstract machine models and instruction set architectures. These essential abstractions enable codesign of hardware and software, and resource estimation for exploring the potential of current and future hardware for computational and simulation tasks. Using these abstractions, we present both new and existing examples that illustrate the benefits of hybrid CV-DV processors relative to traditional DV-only hardware in computation as well as quantum simulation of physical models. Examples include algorithms for transferring states between DV and CV systems, performing the quantum Fourier transform, and simulation of lattice gauge theories. Relative to qubit-only hardware, the bosonic degrees of freedom natively available in hybrid architectures can substantially reduce the circuit complexity of simulations for physical models containing bosons. A key technique is the extension of quantum signal processing ideas to CV-DV systems. This work is intended to serve as a timely and comprehensive guide to this relatively unexplored yet promising approach to quantum computation and to provide a road map to guide future development.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
NASA NTRS1992

Instruction set commutivity

We present a state property called congruence and show how it can be used to demonstrate commutivity of instructions in a modern load-store architecture. Our analysis is particularly important in pipelined microprocessors where instructions are frequently reordered to avoid costly delays in execution caused by hazards. Our work has significant implications to safety and security critical applications since reordering can easily change the meaning and an instruction sequence and current techniques are largely ad hoc. Our work is done in a mechanical theorem prover and results in a set of trustworthy rules for instruction reordering. The mechanization makes it practical to analyze the entire instruction set.

Windley, P.↗
NASA NTRS1993

The effects of instructional sets on reactions to and performance on an intelligent tutoring system

The effects of a contextual factor, i.e., task instructions, on performance on and reactions to an Intellegent Tutoring System (ITS) training Remote Manipulator System (RMS) tasks were examined. The results supported the first prediction that task instructions could be used to successfully induce a mastery versus an achievement orientation. Previous research suggests that a mastery orientation can result in beneficial effects on learning and performance of complex tasks. Furthermore, the results supported the second prediction that a mastery orientation would have beneficial effects on learning and performance as well as affective and cognitive reactions to the ITS tasks. Moreover, the results indicated that a mastery orientation was especially beneficial for the more complex ITS tasks and later in task practice, i.e., when a task was performed for the second time. A mastery orientation is posited to have its beneficial effects by focusing more effort and attention on task performance. Conclusions are drawn with some caution due to the small number of subjects, although the results for these subjects were consistent across multiple trials and multiple measures of performance. ITS designers are urged to consider contextual factors such as task instructions and feedback in terms of their potential to induce a mastery versus an achievement orientation.

Johnson, Debra Steele↗
DOE OSTI2024

Neuromorphic intermediate representation: A unified instruction set for interoperable brain-inspired computing

Abstract Spiking neural networks and neuromorphic hardware platforms that simulate neuronal dynamics are getting wide attention and are being applied to many relevant problems using Machine Learning. Despite a well-established mathematical foundation for neural dynamics, there exists numerous software and hardware solutions and stacks whose variability makes it difficult to reproduce findings. Here, we establish a common reference frame for computations in digital neuromorphic systems, titled Neuromorphic Intermediate Representation (NIR). NIR defines a set of computational and composable model primitives as hybrid systems combining continuous-time dynamics and discrete events. By abstracting away assumptions around discretization and hardware constraints, NIR faithfully captures the computational model, while bridging differences between the evaluated implementation and the underlying mathematical formalism. NIR supports an unprecedented number of neuromorphic systems, which we demonstrate by reproducing three spiking neural network models of different complexity across 7 neuromorphic simulators and 4 digital hardware platforms. NIR decouples the development of neuromorphic hardware and software, enabling interoperability between platforms and improving accessibility to multiple neuromorphic technologies. We believe that NIR is a key next step in brain-inspired hardware-software co-evolution, enabling research towards the implementation of energy efficient computational principles of nervous systems. NIR is available atneuroir.org

Science & Technology - Other Topics↗
NASA NTRS1991

Simplified microprocessor design for VLSI control applications

A design technique for microprocessors combining the simplicity of reduced instruction set computers (RISC's) with the richer instruction sets of complex instruction set computers (CISC's) is presented. They utilize the pipelined instruction decode and datapaths common to RISC's. Instruction invariant data processing sequences which transparently support complex addressing modes permit the formulation of simple control circuitry. Compact implementations are possible since neither complicated controllers nor large register sets are required.

Cameron, K.↗
DOE OSTI2024

SPARCS POD CPU BIOS Settings

Instructions on how to go about setting the BIOS on a SPARCS CPU used in an ATU or Pod.

99 GENERAL AND MISCELLANEOUS↗
DOE OSTI2023

Decoding the EEG patterns induced by sequential finger movement for brain-computer interfaces

Objective In recent years, motor imagery-based brain–computer interfaces (MI-BCIs) have developed rapidly due to their great potential in neurological rehabilitation. However, the controllable instruction set limits its application in daily life. To extend the instruction set, we proposed a novel movement-intention encoding paradigm based on sequential finger movement. Approach Ten subjects participated in the offline experiment. During the experiment, they were required to press a key sequentially [i.e., Left→Left (LL), Right→Right (RR), Left→Right (LR), and Right→Left (RL)] using the left or right index finger at about 1 s intervals under an auditory prompt of 1 Hz. The movement-related cortical potential (MRCP) and event-related desynchronization (ERD) features were used to investigate the electroencephalography (EEG) variation induced by the sequential finger movement tasks. Twelve subjects participated in an online experiment to verify the feasibility of the proposed paradigm. Main results As a result, both the MRCP and ERD features showed the specific temporal–spatial EEG patterns of different sequential finger movement tasks. For the offline experiment, the average classification accuracy of the four tasks was 71.69%, with the highest accuracy of 79.26%. For the online experiment, the average accuracies were 83.33% and 82.71% for LL-versus-RR and LR-versus-RL, respectively. Significance This paper demonstrated the feasibility of the proposed sequential finger movement paradigm through offline and online experiments. This study would be helpful for optimizing the encoding method of motor-related EEG information and providing a promising approach to extending the instruction set of the movement intention-based BCIs.

Liu, Chang↗
NASA NTRS1992

Hypercluster Parallel Processor

Hypercluster computer system includes multiple digital processors, operation of which coordinated through specialized software. Configurable according to various parallel-computing architectures of shared-memory or distributed-memory class, including scalar computer, vector computer, reduced-instruction-set computer, and complex-instruction-set computer. Designed as flexible, relatively inexpensive system that provides single programming and operating environment within which one can investigate effects of various parallel-computing architectures and combinations on performance in solution of complicated problems like those of three-dimensional flows in turbomachines. Hypercluster software and architectural concepts are in public domain.

Blech, Richard A.↗
DOE OSTI2024

Realistic Cost to Execute Practical Quantum Circuits using Direct Clifford+T Lattice Surgery Compilation

We report a resource estimation pipeline that explicitly compiles quantum circuits expressed using the Clifford+T gate set into a surface code lattice surgery instruction set. The cadence of magic state requests from the compiled circuit enables the optimization of magic state distillation and storage requirements in a post-hoc analysis. To compile logical circuits into lattice surgery operations, we build upon the open-source Lattice Surgery Compiler. The revised compiler operates in two stages: the first translates logical gates into an abstract, layout-independent instruction set; the second compiles these into local lattice surgery instructions that are allocated to hardware tiles according to a specified resource layout. The second stage retains logical parallelism while avoiding resource contention in the fault-tolerant layer, aiding realism. Additionally, users can specify dedicated tiles at which magic states are replenished, enabling resource costs from the logical computation to be considered independently from magic state distillation and storage. We demonstrate the applicability of our pipeline to large practical quantum circuits by providing resource estimates for the ground state estimation of molecules. Finally, we find that variable magic state consumption rates in real circuits can cause the resource costs of magic state storage to dominate unless production is varied to suit.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1975

Technical description of space ultra reliable modular computer (SUMC), model 2 B

The design features of the SUMC-2B computer, also called the IBM-HTC are described. It is general purpose digital computer implemented with flexible hardware elements and microprograming to enable low cost customizing to a wide range of applications. It executes the S/360 standard instruction set to maintain problem state compability. Memory technology, extended instruction sets, and I/O channel variations are among the available options.

Source record↗
NASA NTRS1975

Design of a modular digital computer system, CDRL no. D001, final design plan

The engineering breadboard implementation for the CDRL no. D001 modular digital computer system developed during design of the logic system was documented. This effort followed the architecture study completed and documented previously, and was intended to verify the concepts of a fault tolerant, automatically reconfigurable, modular version of the computer system conceived during the architecture study. The system has a microprogrammed 32 bit word length, general register architecture and an instruction set consisting of a subset of the IBM System 360 instruction set plus additional fault tolerance firmware. The following areas were covered: breadboard packaging, central control element, central processing element, memory, input/output processor, and maintenance/status panel and electronics.

Easton, R. A.↗
NASA NTRS1981

Digital image data sets for remote sensing instruction

Several sets of LANDSAT image segments and a set of simple image processing programs operating in batch mode are being used to teach an introductory course in digital image analysis and classification. The image data sets contain only a small number of pixels and can be run quickly on most university computing systems. A number of image data sets derived from the raw spectral bands (smoothed data sets, band ratios and texture data sets) allows the student to examine and include these extracted variables in the classification process. Another data set consists of three registered LANDSAT image segments for three different dates so that the student may experiment with multitemporal data processing. The three LANDSAT scenes used in the class are described and the image data sets available for class exercises are listed.

Eyton, J. R.↗
NASA NTRS1972

A survey of compiler optimization techniques

Major optimization techniques of compilers are described and grouped into three categories: machine dependent, architecture dependent, and architecture independent. Machine-dependent optimizations tend to be local and are performed upon short spans of generated code by using particular properties of an instruction set to reduce the time or space required by a program. Architecture-dependent optimizations are global and are performed while generating code. These optimizations consider the structure of a computer, but not its detailed instruction set. Architecture independent optimizations are also global but are based on analysis of the program flow graph and the dependencies among statements of source program. A conceptual review of a universal optimizer that performs architecture-independent optimizations at source-code level is also presented.

Schneck, P. B.↗
NASA NTRS1989

Optical Firmware

Data-processing system exploits high speeds inherent in optical elements. Instruction sets for different computer operations reside on different external memory chips. Laser diodes activated for each operation generate light, reflected by holographic optical element to designated receptors in arithmetic and logic unit. Pattern of light beams embodies instruction set at given instant. With potential ability to reprogram in real time, conceptual system applicable to task-driven programming or artificial intelligence.

Bergman, Larry A.↗
NASA NTRS1991

Content addressable memory project

The progress on the Rutgers CAM (Content Addressable Memory) Project is described. The overall design of the system is completed at the architectural level and described. The machine is composed of two kinds of cells: (1) the CAM cells which include both memory and processor, and support local processing within each cell; and (2) the tree cells, which have smaller instruction set, and provide global processing over the CAM cells. A parameterized design of the basic CAM cell is completed. Progress was made on the final specification of the CPS. The machine architecture was driven by the design of algorithms whose requirements are reflected in the resulted instruction set(s). A few of these algorithms are described.

Hall, Josh↗