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Packaging Concerns and Techniques for Large Devices: Challenges for Complex Electronics
NASA is going to have to accept the use of non-hermetic packages for complex devices. There are a large number of packaging options available. Space application subjects the packages to stresses that they were probably not designed for (vacuum for instance). NASA has to find a way of having assurance in the integrity of the packages. There are manufacturers interested in qualifying non-hermetic packages to MIL-PRF-38535 Class V. Government space users are agreed that Class V should be for hermetic packages only. NASA is working on a new Class for non-hermetic packages for M38535 Appendix B, "Class Y". Testing for package integrity will be required but can be package specific as described by a Package Integrity Test Plan. The plan is developed by the manufacturer and approved by DSCC and government space.
Aeroflex Technology as Class-Y Demonstrator
Modern space field programmable gate array (FPGA) devices with increased functional density and operational frequency, such as Xilinx Virtex 4 (V4) and S (V5), are packaged in non-hermetic ceramic flip chip forms. These next generation space parts were not qualified to the MIL-PRF-38535 Qualified Manufacturer Listing (QML) class-V when they were released because class-V was only intended for hermetic parts. In order to bring Xilinx V5 type packages into the QML system, it was suggested that class-Y be set up as a new category. From 2010 through 2014, a JEDEC G12 task group developed screening and qualification requirements for Class-Y products. The Document Standardization Division of the Defense Logistics Agency (DLA) has completed an engineering practice study. In parallel with the class-Y efforts, the NASA Electronic Parts and Packaging (NEPP) program has funded JPL to study potential reliability issues of the class-Y products. The major hurdle of this task was the absence of adequate research samples. Figure 1-1 shows schematic diagrams of typical structures of class-Y type products. Typically, class-Y products are either in ceramic flip chip column grid array (CGA) or land grid array (LGA) form. In class-Y packages, underfill and heat spread adhesive materials are directly exposed to the spacecraft environment due to their non-hermeticity. One of the concerns originally raised was that the underfill material could degrade due to the spacecraft environment and negatively impact the reliability of the package. In order to study such issues, it was necessary to use ceramic daisy chain flip chip package samples so that continuity of flip chip solder bumps could be monitored during the reliability tests. However, none of the commercially available class-Y daisy chain parts had electrical connections through flip chip solder bumps; only solder columns were daisy chained, which made it impossible to test continuity of flip chip solder bumps without using extremely costly functional parts. Among space parts manufacturers who were interested in producing class-Y products, Aeroflex Microelectronic Solutions-HiRel had been developing assembly processes using their internal R&D classy type samples. In early 2012, JPL and Aeroflex initiated a collaboration to study reliability of the Aeroflex technology as a class-Y demonstrator.
NASA Feedback to DLA Land & Maritime Moratorium on Wafer Fab Audits
On September 29, 2017 the Defense Logistics Agency (DLA), Land and Maritime, announced that on September 1, 2017 they had begun a moratorium on the auditing of wafer fabrication facilities (fabs) used in the production of semiconductor die for military (MIL) qualified integrated circuits and discrete semiconductors (transistors and diodes). The announcement said the moratorium would last for six months initially and would apply to all wafer fabs qualified to MIL-PRF-19500 (discretes) and MIL-PRF-38535 (ICs) located, onshore or offshore. The stated rationale behind this action was to give DLA time to evaluate the risk of modifying current surveillance practices across 70+ Federal Stock Classes (FSC) under the jurisdiction of the DLA Qualifying Activity (VQ). The objective was to free up the resources used in these audits so they could be redirected towards audits of other commodities which were under resourced, notably connectors. In the announcement letter, DLA-VQ requested data from the community to assist with decisions on wafer fab re-audit cycle modifications. NASA used available information on current and historical audit schedules to gather such data and analyzed it to provide an in-depth understanding of the impact of locations, part types, in-house or out-of-house fabs on those schedules over time. This presentation provides the results of NASA's data analysis and suggest some changes to auditing practices that could increase efficient use of resources without significant increases in risk.