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Ultra‐Steep Slope Impact Ionization Transistors Based on Graphene/InAs Heterostructures
With the continued scaling of transistors, there is a growing trend for developing steep slope transistors with subthreshold swing (SS) below Boltzmann limitation ( k T/ q ). To this end, impact ionization metal oxide semiconductor (I‐MOS) transistors are attractive for a unique combination of high ON‐state current density, small hysteresis, and ultra‐steep SS slope. However, the performance of I‐MOS is generally limited by the relatively thick depletion region and large operation voltage required for the activation of impact ionization (typically >5 V). Herein, a high‐performance I‐MOS is constructed by van der Waals integrating single‐crystal InAs film with graphene. Due to the low bandgap of InAs as well as the semi‐metallic nature of graphene, the InAs/graphene I‐MOS demonstrates a low operation voltage of 1.5 V, high ON‐state current of 230 μA μm −1 , steep SS <0.6 mV dec −1 , and large ON–OFF ratio >10 6 at temperature below 200 K. Furthermore, a negative transconductance and steep current oscillation is observed in the subthreshold regime, and a device working mechanism is proposed for this novel phenomenon. This study not only pushes the performance limit of I‐MOS but also defines a general pathway to van der Waals heterostructures between conventional III–V compound semiconductors and novel 2D materials for unconventional device functions.
Enhancing mobility and interface state engineering via UV-ozone treatment in BEOL-compatible ultrathin TiO 2 transistors
It has emerged as a potential candidate to improve the performance of monolithic-three-dimensional (M3D) integration of fused logic and memories through low-temperature in situ synthesis of high-performance metal–oxide–semiconductor (MOS) transistors. Here, we report the demonstration of the BEOL-compatible low thermal budget (350 °C) fabrication process of ultrathin-TiO2 transistors by the combination of RTA and UV-ozone treatment (RTA-UVOz). UV–ozone (UVOz) treatment of TiO2 anatase films significantly enhances stability, boosting ION current and field effect mobility (μ FE ) by two times of magnitude in TiO2 TFTs. UV ozone treatment helps to eliminate pre-existing oxygen vacancies and carbon contamination on TiO2 channels even at low temperature (100 °C), resulting in high-quality channel/dielectric interfaces with low interface states (D it ). During UVOz treatment, oxygen species (O x ) passivate the oxygen vacancies ($V$$^{2+}_{o}$), and hence low concentration of $V$$^{2+}_{o}$ would be left for ionization/de-ionization under PBS/NBS, leading to improved bias stress stability. Furthermore, the TiO 2 TFTs with thin ZrO 2 gate dielectric exhibited excellent performance including a lower subthreshold swing (SS) of 98 mV/dec with high drive I ON current ∼ 4.5 μA/μm, a high I ON /I OFF > 10 9 , and mobility μFE of 7 cm 2 /V-s under a battery powered voltage of 1 V. UV–ozone treatment enables high-performance, CMOS-compatible TiO 2 transistors with a low thermal budget, ideal for next-generation flexible, energy-efficient electronics.
Molybdenum Contacts to MoS 2 Field‐Effect Transistors: Schottky Barrier Extraction, Electrical Transport, and Low‐Frequency Noise
MoS 2 has great interest for nanoscale electronic devices, including transistors and sensors. Defect‐free structure, clean interface with the gate dielectric, and metals with suitable metal–semiconductor junctions are key for reliable devices. Molybdenum is shown as an excellent electrode for MoS 2 field‐effect transistors (FETs), but the correlation among device current, field‐effect mobility, and the low‐frequency noise (LFN) with number of atomic layers is not studied. Furthermore, the impact of Mo/MoS 2 Schottky barrier on electronic injection and scattering in the device needs to be understood. Herein, by studying the FETs with channels of different numbers of atomic‐layer thicknesses, it is shown that a molybdenum metal contact to MoS 2 provides reliable current injection with low Schottky barrier height, low contact resistance, low electron–phonon scattering, and negligible impurity scattering. The mobility and LFN are optimal at a channel thickness of ≈12 atomic layers, which is consistent with the “mobility maximum window” in MoS 2 transistors with prior studies using other contact metals.
High broadband photoconductivity of few-layered MoS 2 field-effect transistors measured using multi-terminal methods: effects of contact resistance
Among the layered two dimensional semiconductors, molybdenum disulfide (MoS 2 ) is considered to be an excellent candidate for applications in optoelectronics and integrated circuits due to its layer-dependent tunable bandgap in the visible region, high ON/OFF current ratio in field-effect transistors (FET) and strong light–matter interaction properties. In this study, using multi-terminal measurements, we report high broadband photocurrent response ( R ) and external quantum efficiency (EQE) of few-atomic layered MoS 2 phototransistors fabricated on a SiO 2 dielectric substrate and encapsulated with a thin transparent polymer film of Cytop. The photocurrent response was measured using a white light source as well as a monochromatic light of wavelength λ = 400 nm–900 nm. We measured responsivity using a 2-terminal configuration as high as R = 1 × 10 3 A W -1 under white light illumination with an optical power P opt = 0.02 nW. The R value increased to 3.5 × 10 3 A W -1 when measured using a 4-terminal configuration. Using monochromatic light on the same device, the measured values of R were 10 3 and 6 × 10 3 A W -1 under illumination of λ = 400 nm when measured using 2- and 4-terminal methods, respectively. The highest EQE values obtained using λ = 400 nm were 10 5 % and 10 6 % measured using 2- and 4-terminal configurations, respectively. The wavelength dependent responsivity decreased from 400 nm to the near-IR region at 900 nm. The observed photoresponse, photocurrent–dark current ratio (PDCR), detectivity as a function of applied gate voltage, optical power, contact resistances and wavelength were measured and are discussed in detail. The observed responsivity is also thoroughly studied as a function of contact resistance of the device.
Towards Low-Temperature CVD Synthesis and Characterization of Mono- or Few-Layer Molybdenum Disulfide
Molybdenum disulfide (MoS 2 ) transistors are a promising alternative for the semiconductor industry due to their large on/off current ratio (>10 10 ), immunity to short-channel effects, and unique switching characteristics. MoS 2 has drawn considerable interest due to its intriguing electrical, optical, sensing, and catalytic properties. Monolayer MoS 2 is a semiconducting material with a direct band gap of ~1.9 eV, which can be tuned. Commercially, the aim of synthesizing a novel material is to grow high-quality samples over a large area and at a low cost. Although chemical vapor deposition (CVD) growth techniques are associated with a low-cost pathway and large-area material growth, a drawback concerns meeting the high crystalline quality required for nanoelectronic and optoelectronic applications. This research presents a lower-temperature CVD for the repeatable synthesis of large-size mono- or few-layer MoS 2 using the direct vapor phase sulfurization of MoO 3 . The samples grown on Si/SiO 2 substrates demonstrate a uniform single-crystalline quality in Raman spectroscopy, photoluminescence (PL), scanning electron microscopy (SEM), atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), and scanning transmission electron microscopy. These characterization techniques were targeted to confirm the uniform thickness, stoichiometry, and lattice spacing of the MoS 2 layers. The MoS 2 crystals were deposited over the entire surface of the sample substrate. With a detailed discussion of the CVD setup and an explanation of the process parameters that influence nucleation and growth, this work opens a new platform for the repeatable synthesis of highly crystalline mono- or few-layer MoS 2 suitable for optoelectronic application.
Domain wall enabled steep slope switching in MoS2 transistors towards hysteresis-free operation
Abstract The device concept of ferroelectric-based negative capacitance (NC) transistors offers a promising route for achieving energy-efficient logic applications that can outperform the conventional semiconductor technology, while viable operation mechanisms remain a central topic of debate. In this work, we report steep slope switching in MoS 2 transistors back-gated by single-layer polycrystalline PbZr 0.35 Ti 0.65 O 3 . The devices exhibit current switching ratios up to 8 × 10 6 within an ultra-low gate voltage window of $$V_{{{\mathrm{g}}}} = \pm \! 0.5$$ V g = ± 0.5 V and subthreshold swing (SS) as low as 9.7 mV decade −1 at room temperature, transcending the 60 mV decade −1 Boltzmann limit without involving additional dielectric layers. Theoretical modeling reveals the dominant role of the metastable polar states within domain walls in enabling the NC mode, which is corroborated by the relation between SS and domain wall density. Our findings shed light on a hysteresis-free mechanism for NC operation, providing a simple yet effective material strategy for developing low-power 2D nanoelectronics.
Probing the Electronic and Opto-Electronic Properties of Multilayer MoS 2 Field-Effect Transistors at Low Temperatures
Transition metal dichalcogenides (TMDs)-based field-effect transistors (FETs) are being investigated vigorously for their promising applications in optoelectronics. Despite the high optical response reported in the literature, most of them are studied at room temperature. To extend the application of these materials in a photodetector, particularly at a low temperature, detailed understanding of the photo response behavior of these materials at low temperatures is crucial. Here we present a systematic investigation of temperature-dependent electronic and optoelectronic properties of few-layers MoS 2 FETs, synthesized using the mechanical exfoliation of bulk MoS 2 crystal, on the Si/SiO 2 substrate. Our MoS 2 FET show a room-temperature field-effect mobility μ FE ~40 cm 2 ·V -1 ·s -1 , which increases with decreasing temperature, stabilizing at 80 cm 2 ·V -1 ·s -1 below 100 K. The temperature-dependent (50 K < T < 300 K) photoconductivity measurements were investigated using a continuous laser source λ = 658 nm (E = 1.88 eV) over a broad range of effective illuminating laser intensity, P eff (0.02 μW < P eff < 0.6 μW). Photoconductivity measurements indicate a fractional power dependence of the steady-state photocurrent. The room-temperature photoresponsivity (R) obtained in these samples was found to be ~2 AW -1 , and it increases as a function of decreasing temperature, reaching a maximum at T = 75 K. The optoelectronic properties of MoS 2 at a low temperature give an insight into photocurrent generation mechanisms, which will help in altering/improving the performance of TMD-based devices for various applications.
Biaxial Tensile Strain Enhances Electron Mobility of Monolayer Transition Metal Dichalcogenides
Strain engineering can modulate the material properties of two-dimensional (2D) sem- iconductors for electronic and optoelectronic applications. Recent theory and experiments have found that uniaxial tensile strain can improve the electron mobility of monolayer MoS 2 , a 2D semiconductor, but the effects of biaxial strain on charge transport are not well-understood in 2D semiconductors. Here, we use biaxial tensile strain on flexible substrates to probe the electron mobility in monolayer WS 2 and MoS 2 transistors. Further, this approach experimentally achieves ~2× higher on-state current and mobility with ~0.3% applied biaxial strain in WS 2 , the highest mobility improvement at the lowest strain reported to date. We also examine the mechanisms behind this improvement through density functional theory simulations, concluding that the enhancement is primarily due to reduced intervalley electron-phonon scattering. These results underscore the role of strain engineering 2D semiconductors for flexible electronics, sensors, integrated circuits, and other opto-electronic applications.
Low-thermal-budget synthesis of monolayer molybdenum disulfide for silicon back-end-of-line integration on a 200 mm platform
Two-dimensional (2D) materials are promising candidates for future electronics due to their excellent electrical and photonic properties. Although promising results on the wafer-scale synthesis (≤150 mm diameter) of monolayer molybdenum disulfide (MoS 2 ) have already been reported, the high-quality synthesis of 2D materials on wafers of 200 mm or larger, which are typically used in commercial silicon foundries, remains difficult. The back-end-of-line (BEOL) integration of directly grown 2D materials on silicon complementary metal–oxide–semiconductor (CMOS) circuits is also unavailable due to the high thermal budget required, which far exceeds the limits of silicon BEOL integration (<400 °C). This high temperature forces the use of challenging transfer processes, which tend to introduce defects and contamination to both the 2D materials and the BEOL circuits. Here we report a low-thermal-budget synthesis method (growth temperature < 300 °C, growth time ≤ 60 min) for monolayer MoS 2 films, which enables the 2D material to be synthesized at a temperature below the precursor decomposition temperature and grown directly on silicon CMOS circuits without requiring any transfer process. We designed a metal–organic chemical vapour deposition reactor to separate the low-temperature growth region from the high-temperature chalcogenide-precursor-decomposition region. We obtain monolayer MoS 2 with electrical uniformity on 200 mm wafers, as well as a high material quality with an electron mobility of ~35.9 cm 2 V -1 s -1 . Finally, we demonstrate a silicon-CMOS-compatible BEOL fabrication process flow for MoS 2 transistors; the performance of these silicon devices shows negligible degradation (current variation < 0.5%, threshold voltage shift < 20 mV). We believe that this is an important step towards monolithic 3D integration for future electronics.
Superionic fluoride gate dielectrics with low diffusion barrier for two-dimensional electronics
Exploration of new dielectrics with a large capacitive coupling is an essential topic in modern electronics when conventional dielectrics suffer from the leakage issue near the breakdown limit. Here, to address this looming challenge, we demonstrate that rare-earth metal fluorides with extremely low ion migration barriers can generally exhibit an excellent capacitive coupling over 20 μF cm -2 (with an equivalent oxide thickness of ~0.15 nm and a large effective dielectric constant near 30) and great compatibility with scalable device manufacturing processes. Such a static dielectric capability of superionic fluorides is exemplified by MoS 2 transistors exhibiting high on/off current ratios over 10 8 , ultralow subthreshold swing of 65 mV dec -1 and ultralow leakage current density of ~10 -6 A cm -2 . Therefore, the fluoride-gated logic inverters can achieve notably higher static voltage gain values (surpassing ~167) compared with a conventional dielectric. Furthermore, the application of fluoride gating enables the demonstration of NAND, NOR, AND and OR logic circuits with low static energy consumption. In particular, the superconductor–insulator transition at the clean-limit Bi 2 Sr 2 CaCu 2 O 8+δ can also be realized through fluoride gating. In conclusion, our findings highlight fluoride dielectrics as a pioneering platform for advanced electronic applications and for tailoring emergent electronic states in condensed matter.
Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad
According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad around a reactor in-core required. In harsh radiating environments such as NPPs, sensors such as micro-pocket-fission detectors (MPFD) would be a promising technology to be operated for detecting neutrons in reactor cores. For those sensors, readout circuits should be fundamentally placed close to sensing devices for minimizing signal interferences and white noise. Therefore, radiation hardening ability is necessary for the circuits under high radiation environments. This paper presents various integrated circuit designs for a radiation hardened charge-sensitive amplifier (CSA) by using SiGe 130 nm and Si 180 nm fabrication processes with different channel widths and transistor types of complementary metal-oxide-semiconductor (CMOS) and bipolar CMOS (BiCMOS). These circuits were tested under γ–ray environment with Cobalt-60 of high level activity: 490 kCi. The experiment results indicate amplitude degradation of 2.85%–34.3%, fall time increase of 201–1730 ns, as well as a signal-to-noise ratio (SNR) of 0.07–11.6 dB decrease with irradiation dose increase. These results can provide design guidelines for radiation hardening operational amplifiers in terms of transistor sizes and structures.
Quantifying carrier density in monolayer MoS 2 by optical spectroscopy
The successful design and device integration of nanoscale heterointerfaces hinges upon precise manipulation of both ground- and excited-state charge carrier (electron and hole) densities. However, it is particularly challenging to quantify these charge carrier densities in nanoscale materials, leading to uncertainties in the mechanisms of many carrier density-dependent properties and processes. Here, we demonstrate a method that utilizes steady-state and transient absorption spectroscopies to correlate monolayer MoS 2 electron density with the easily measured metric of excitonic optical absorption quenching in a variety of mixed-dimensionality s-SWCNT/MoS 2 heterostructures. By employing a 2D phase-space filling model, the resulting correlation elucidates the relationship between charge density, local dielectric environment, and concomitant excitonic properties. The phase-space filling model is also able to describe existing trends from the literature on transistor-based measurements on MoS 2 , WS 2 , and MoSe 2 monolayers that were not previously compared to a physical model, providing additional support for our method and results. The findings provide a pathway to the community for estimating both ground- and excited-state carrier densities in a wide range of TMDC-based systems.
Solid-state thermometry via ionic–electronic coupling in two-dimensional heterostructures
The coupling of ionic and electronic transport in solid-state systems offers new opportunities for realizing compact, energy-efficient sensing technologies, yet practical implementations remain limited. In this article, we introduce a two-dimensional iontronic platform based on field-effect transistors that integrate monolayer MoS 2 channels with van der Waals bimetallic thiophosphates ( AB P 2 X 6 , A = Li, Cu, Ag and so on; B = In, Sc and so on; and X = S and Se) as ionic gate dielectrics to realize on-chip thermometry. Specifically, we exploit thermally activated ion migration within the gate dielectric leading to conductance modulation in the MoS 2 channel for temperature sensing. We achieve ~1–2 °C resolution, fast electronic readout and subpicojoule energy consumption in an ultracompact footprint (~1 µm 2 ). Beyond thermometry, these results establish bimetallic thiophosphates as a versatile platform for solid-state iontronics and broaden the functional design space of van der Waals heterostructures for sensing, actuation and adaptive electronics.
Selected Area Manipulation of MoS 2 via Focused Electron Beam-Induced Etching for Nanoscale Device Editing
Here we demonstrate direct-write patterning of single and multilayer MoS 2 via a focused electron beam-induced etching (FEBIE) process mediated with the XeF 2 precursor. MoS 2 etching is performed at various currents, areal doses, on different substrates, and characterized using scanning electron and atomic force microscopies as well as Raman and photoluminescence spectroscopies. Scanning transmission electron microscopy reveals a sub-40 nm etching resolution and the progression of point defects and lateral etching of the consequent unsaturated bonds. The results confirm that the electron beam-induced etching process is minimally invasive to the underlying material in comparison to ion beam techniques, which damage the subsurface material. Single-layer MoS 2 field-effect transistors are fabricated, and device characteristics are compared for channels that are edited via the selected area etching process. The source–drain current at constant gate and source–drain voltage scale linearly with the edited channel width. Moreover, the mobility of the narrowest channel width decreases, suggesting that backscattered and secondary electrons collaterally affect the periphery of the removed area. Focused electron beam doses on single-layer transistors below the etching threshold were also explored as a means to modify/thin the channel layer. The FEBIE exposures showed demonstrative effects via the transistor transfer characteristics, photoluminescence spectroscopy, and Raman spectroscopy. While strategies to minimize backscattered and secondary electron interactions outside of the scanned regions require further investigation, here, we show that FEBIE is a viable approach for selective nanoscale editing of MoS 2 devices.
Characterizing Defects Inside Hexagonal Boron Nitride Using Random Telegraph Signals in van der Waals 2D Transistors
Single-crystal hexagonal boron nitride (hBN) is used extensively in many two-dimensional electronic and quantum devices, where defects significantly impact performance. Therefore, characterizing and engineering hBN defects are crucial for advancing these technologies. Here, we examine the capture and emission dynamics of defects in hBN by utilizing low-frequency noise (LFN) spectroscopy in hBN-encapsulated and graphene-contacted MoS 2 field-effect transistors (FETs). The low disorder of this heterostructure allows the detection of random telegraph signals (RTS) in large device dimensions of 100 μm 2 at cryogenic temperatures. Analysis of gate bias- and temperature-dependent LFN data indicate that RTS originates from a single trap species within hBN. By performing multi-space density functional theory (MS-DFT) calculations on a gated defective hBN/MoS 2 heterostructure model, we assign substitutional carbon atoms in boron sites as the atomistic origin of RTS. This study demonstrates the utility of LFN spectroscopy combined with MS-DFT analysis on a low-disorder all-vdW FET as a powerful means for characterizing the atomistic defects in single-crystal hBN.
Low Ohmic contact resistance and high on/off ratio in transition metal dichalcogenides field-effect transistors via residue-free transfer
Beyond-silicon technology demands ultrahigh performance field-effect transistors. Transition metal dichalcogenides provide an ideal material platform, but the device performances such as the contact resistance, on/off ratio and mobility are often limited by the presence of interfacial residues caused by transfer procedures. Here, we show an ideal residue-free transfer approach using polypropylene carbonate with a negligible residue coverage of ~0.08% for monolayer MoS 2 at the centimetre scale. By incorporating a bismuth semimetal contact with an atomically clean monolayer MoS 2 field-effect transistor on hexagonal boron nitride substrate, we obtain an ultralow Ohmic contact resistance of ~78 Ω µm, approaching the quantum limit, and a record-high on/off ratio of ~10 11 at 15 K. Further, such an ultra-clean fabrication approach could be the ideal platform for high-performance electrical devices using large-area semiconducting transition metal dichalcogenides.