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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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16 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1993

Two- and Three-dimensional High Performance, Patterned Overlay Multi-chip Module Technology

A two- and three-dimensional multi-chip module technology was developed in response to the continuum in demand for increased performance in electronic systems, as well as the desire to reduce the size, weight, and power of space systems. Though developed to satisfy the needs of military programs, such as the Strategic Defense Initiative Organization, the technology, referred to as High Density Interconnect, can also be advantageously exploited for a wide variety of commercial applications, ranging from computer workstations to instrumentation and microwave telecommunications. The robustness of the technology, as well as its high performance, make this generality in application possible. More encouraging is the possibility of this technology for achieving low cost through high volume usage.

Lyke, James↗
NASA NTRS1995

Compact Multimedia Systems in Multi-chip Module Technology

This tutorial paper shows advanced multimedia system designs based on multi-chip module (MCM) technologies that provide essential computing, compression, communication, and storage capabilities for various large scale information highway applications.!.

Multi-Chip Module Technology↗
NASA NTRS1996

Development of the command data system and ground software for the SEDSAT-1 microsatellite

SEDSAT-1 is designed to be a low cost scientific satellite which is to be used to perform a minimum of five tasks which include: (1) the acquisition of a number of important parameters associated with the tethering processes from the payloads perspective (such as accelerations incurred and imaging data of the tether during deployment), (2) to act as a remote sensing platform for making measurements of the Earth's Atmosphere (allowing research to be performed in such areas as vertical lightning observation, visible light spectrography, and cloud cover studies, (3) to act as a general purpose amateur radio communication satellite relaying information back to earth, (4) to demonstrate the feasibility of the deployment in low earth orbit of advanced technology such as the Gallium Arsenide Solar Cells, Nickel Metal Hydride batteries, and multi-chip module technology and, (5) to support student's active participation in applying the disciplines of engineering and science to space-based hardware platforms. The project includes the Three-axis Accelerometer System, TAS, Experiment which is designed to report the accelerations that the satellite undergoes during the tethering operations and during the second phase of the mission when the free floating satellite comes in contact with orbit debris. The SEASIS (SEDS Earth, Atmosphere, and Space Imaging System) is another SEDSAT experiment designed to provide images of the tether during its deployment and the earth during the second phase of the mission. To control these experiments and virtually all other satellite operations the Command Data System, CDS is employed. This system utilizes a moderate complexity micro-controller controlled by tasks operating under a real-time operating system to dynamically monitor and control the satellite. The scope of this researchers efforts has been in the general area of coordinating and assisting the student researchers with the development of the CDS and ground station interfaces. This included the low level CDS hardware design and the formulization of a general software plan and schedule for both the CDS and ground station portions of the project.

Wells, B. Earl↗
NASA NTRS1996

Chip-on-Board Technology 1996 Year-end Report (Design, Manufacturing, and Reliability Study)

The major impetus for flight qualifying Chip-On-Board (COB) packaging technology is the shift in emphasis for space missions to smaller, better, and cheaper spacecraft and satellites resulting from the NASA New Millenium initiative and similar requirements in DoD-sponsored programs. The most important benefit that can potentially be derived from miniaturizing spacecraft and satellites is the significant cost saving realizable if a smaller launch vehicle may be employed. Besides the program cost saving, there are several other advantages to building COB-based space hardware. First, once a well-controlled process is established, COB can be low cost compared to standard Multi-Chip Module (MCM) technology. This cost competitiveness is regarded as a result of the generally greater availability and lower cost of Known Good Die (KGD). Coupled with the elimination of the first level of packaging (chip package), compact, high-density circuit boards can be realized with Printed Wiring Boards (PWB) that can now be made with ever-decreasing feature size in line width and via hole. Since the COB packaging technique in this study is based mainly on populating bare dice on a suitable multi-layer laminate substrate which is not hermetically sealed, die coating for protection from the environment is required. In recent years, significant improvements have been made in die coating materials which further enhance the appeal of COB. Hysol epoxies, silicone, parylene and silicon nitride are desirable because of their compatible Thermal Coefficient of Expansion (TCE) and good moisture resistant capability. These die coating materials have all been used in the space and other industries with varying degrees of success. COB technology, specifically siliconnitride coated hardware, has been flown by Lockheed on the Polar satellite. In addition, DARPA has invested a substantial amount of resources on MCM and COB-related activities recently. With COB on the verge of becoming a dominant player in DoD programs, DARPA is increasing its support of the availability of KGDs which will help decrease their cost. Aside from the various major developments and trends in the space and defense industries that are favorable to the acceptance and widespread use of'COB packaging technology, implementing COB can be appealing in other aspects. Since the interconnection interface is usually the weak link in a system, the overall circuit or system reliability may actually be improved because of the elimination of a level of interconnect/packaging at the chip. With COB, mixing packaging technologies is possible. Because some devices are only available in commercial plastic packages, populating a multi-layer laminate substrate with both bare dice and plastic-package parts is inevitable. Another attractive feature of COB is that re-workability is possible if die coating is applied only on the die top. This method allows local replacement of individual dice that were found to be defective instead of replacing an entire board. In terms of thermal management, unpackaged devices offer a shorter thermal resistance path than their packaged counterparts thereby improving thermal sinking and heat removal from the parts.

Le, Binh Q.↗
NASA NTRS1993

Spacecraft computer technology at Southwest Research Institute

Southwest Research Institute (SwRI) has developed and delivered spacecraft computers for a number of different near-Earth-orbit spacecraft including shuttle experiments and SDIO free-flyer experiments. We describe the evolution of the basic SwRI spacecraft computer design from those weighing in at 20 to 25 lb and using 20 to 30 W to newer models weighing less than 5 lb and using only about 5 W, yet delivering twice the processing throughput. Because of their reduced size, weight, and power, these newer designs are especially applicable to planetary instrument requirements. The basis of our design evolution has been the availability of more powerful processor chip sets and the development of higher density packaging technology, coupled with more aggressive design strategies in incorporating high-density FPGA technology and use of high-density memory chips. In addition to reductions in size, weight, and power, the newer designs also address the necessity of survival in the harsh radiation environment of space. Spurred by participation in such programs as MSTI, LACE, RME, Delta 181, Delta Star, and RADARSAT, our designs have evolved in response to program demands to be small, low-powered units, radiation tolerant enough to be suitable for both Earth-orbit microsats and for planetary instruments. Present designs already include MIL-STD-1750 and Multi-Chip Module (MCM) technology with near-term plans to include RISC processors and higher-density MCM's. Long term plans include development of whole-core processors on one or two MCM's.

Shirley, D. J.↗
NASA NTRS2020

Cold Survivable Current Sense Multi-Chip Module

This paper will present the design of a Current Sense Module (CSM) used to measure motor phase currents that is capable of surviving the harsh ambient environment of ocean worlds, such as Europa and Enceladus. The CSM module is fabricated by i3 Electronics using their Multi-Chip Module (MCM) technology with techniques developed by JPL to allow this module to survive temperatures down to -184°C. This module greatly improves the ability to measure phase and bridge current which can be problematic in extreme environments. In addition, by packaging these electronics at the die level, we achieve significant weight and size savings. This module is one of several modules that employ similar techniques that are integrated into a distributed or centralized motor controller. This paper will discuss the module’s design along with a summary of our test results.

Cheng, Ben↗
NASA NTRS1992

Low energy CMOS for space applications

The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

Panwar, Ramesh↗
NASA NTRS2003

The Neptune/Triton Explorer Mission: A Concept Feasibility Study

Technological advances over the next 10 to 15 years promise to enable a number of smaller, more capable science missions to the outer planets. With the inception of miniaturized spacecraft for a wide range of applications, both in large clusters around Earth, and for deep space missions, NASA is currently in the process of redefining the way science is being gathered. Technologies such as 3-Dimensional Multi-Chip Modules, Micro-machined Electromechanical Devices, Multi Functional Structures, miniaturized transponders, miniaturized propulsion systems, variable emissivity thermal coatings, and artificial intelligence systems are currently in research and development, and are scheduled to fly (or have flown) in a number of missions. This study will leverage on these and other technologies in the design of a lightweight Neptune orbiter unlike any other that has been proposed to date. The Neptune/Triton Explorer (NExTEP) spacecraft uses solar electric earth gravity assist and aero capture maneuvers to achieve its intended target orbit. Either a Taurus or Delta-class launch vehicle may be used to accomplish the mission.

Esper, Jaime↗
NASA NTRS2017

Interconnect and Packaging Technologies for Terahertz Communication Systems

Using newly developed silicon micromachining technology that enables low-loss and highly integrated packaging solutions, we are developing vertically stacked transmitters and receivers at terahertz frequencies that can be used for communication and other terahertz systems. Although there are multiple ways to address the problem of interconnect and packaging solutions at these frequencies, such as system-on-package (SOP), multi-chip modules (MCM), substrate integrated waveguide (SIW), liquid crystal polymer (LCP) based multilayer technologies, and others, we show that deep reactive ion etching (DRIE) based silicon micromachining with vertical integration allows the most effective solutions at terahertz frequencies.

Micromachining↗
NASA NTRS2010

Miniature MMIC Low Mass/Power Radiometer Modules for the 180 GHz GeoSTAR Array

We have developed and demonstrated miniature 180 GHz Monolithic Microwave Integrated Circuit (MMIC) radiometer modules that have low noise temperature, low mass and low power consumption. These modules will enable the Geostationary Synthetic Thinned Aperture Radiometer (GeoSTAR) of the Precipitation and All-weather Temperature and Humidity (PATH) Mission for atmospheric temperature and humidity profiling. The GeoSTAR instrument has an array of hundreds of receivers. Technology that was developed included Indium Phosphide (InP) MMIC Low Noise Amplifiers (LNAs) and second harmonic MMIC mixers and I-Q mixers, surface mount Multi-Chip Module (MCM) packages at 180 GHz, and interferometric array at 180 GHz. A complete MMIC chip set for the 180 GHz receiver modules (LNAs and I-Q Second harmonic mixer) was developed. The MMIC LNAs had more than 50% lower noise temperature (NT=300K) than previous state-of-art and MMIC I-Q mixers demonstrated low LO power (3 dBm). Two lots of MMIC wafers were processed with very high DC transconductance of up to 2800 mS/mm for the 35 nm gate length devices. Based on these MMICs a 180 GHz Multichip Module was developed that had a factor of 100 lower mass/volume (16x18x4.5 mm3, 3g) than previous generation 180 GHz receivers.

Monolithic Microwave Integrated Circuit (MMIC)↗
NASA NTRS1995

Advanced flight computer. Special study

This report documents a special study to define a 32-bit radiation hardened, SEU tolerant flight computer architecture, and to investigate current or near-term technologies and development efforts that contribute to the Advanced Flight Computer (AFC) design and development. An AFC processing node architecture is defined. Each node may consist of a multi-chip processor as needed. The modular, building block approach uses VLSI technology and packaging methods that demonstrate a feasible AFC module in 1998 that meets that AFC goals. The defined architecture and approach demonstrate a clear low-risk, low-cost path to the 1998 production goal, with intermediate prototypes in 1996.

Coo, Dennis↗
NASA NTRS1996

Ka-Band Tiny Transmitter for the New Millenium Program

The size, mass and cost of telecommunications systems on deep space missions have increased at almost an exponential rate over the last thirty years. Great cost and size reduction of these systems can be achieved by reducing the cost and size of the transponder component of the radio subsystem. An advanced technology X-and Ka-band (8 and 32 GHz) Tiny Transmitter is being developed at JPL for the New Millenium program and is described in this paper.

Cassini↗
NASA NTRS1994

Flexible manufacturing for photonics device assembly

The assembly of photonics devices such as laser diodes, optical modulators, and opto-electronics multi-chip modules (OEMCM), usually requires the placement of micron size devices such as laser diodes, and sub-micron precision attachment between optical fibers and diodes or waveguide modulators (usually referred to as pigtailing). This is a very labor intensive process. Studies done by the opto-electronics (OE) industry have shown that 95 percent of the cost of a pigtailed photonic device is due to the use of manual alignment and bonding techniques, which is the current practice in industry. At Lawrence Livermore National Laboratory, we are working to reduce the cost of packaging OE devices through the use of automation. Our efforts are concentrated on several areas that are directly related to an automated process. This paper will focus on our progress in two of those areas, in particular, an automated fiber pigtailing machine and silicon micro-technology compatible with an automated process.

Lu, Shin-Yee↗
NASA NTRS1997

A Novel Silicon Micromachined Integrated MCM Thermal Management System

"Micromachining" is a chemical means of etching three-dimensional structures, typically in single- crystalline silicon. These techniques are leading toward what is coming to be referred to as MEMS (Micro Electro Mechanical Systems), where in addition to the ordinary two-dimensional (planar) microelectronics, it is possible to build three-dimensional n-ticromotors, electrically- actuated raicrovalves, hydraulic systems and much more on the same microchip. These techniques become possible because of differential etching rates of various crystallographic planes and materials used for semiconductor n-ticrofabfication. The University of Cincinnati group in collaboration with Karl Baker at NASA Lewis were the first to form micro heat pipes in silicon by the above techniques. Current work now in progress using MEMS technology is now directed towards the development of the next generation in MCM (Multi Chip Module) packaging. Here we propose to develop a complete electronic thermal management system which will allow densifica6on in chip stacking by perhaps two orders of magnitude. Furthermore the proposed technique will allow ordinary conu-nercial integrated chips to be utilized. Basically, the new technique involves etching square holes into a silicon substrate and then inserting and bonding commercially available integrated chips into these holes. For example, over a 100 1/4 in. by 1 /4 in. integrated chips can be placed on a 4 in. by 4 in. silicon substrate to form a Multi-Chip Module (MCM). Placing these MCM's in-line within an integrated rack then allows for three-diniensional stacking. Increased miniaturization of microelectronic circuits will lead to very high local heat fluxes. A high performance thermal management system will be specifically designed to remove the generated energy. More specifically, a compact heat exchanger with milli / microchannels will be developed and tested to remove the heat through the back side of this MCM assembly for moderate and high heat flux applications, respectively. The high heat load application of particular interest in mind is the motor controller developed by Martin Marietta for Nasa to control the thruster's directional actuators on space vechicles. Work is also proposed to develop highly advanced and improved porous wick structures for use in advanced heat loops. The porous wick will be micromachined from silicon using MEMS technology, thus permitting far superior control of pore size and pore distribution (over wicks made from sintered n-ietals), which in turn is expected to led to significantly improved heat loop performance.

Kazmierczak, M. J.↗
NASA NTRS2009

NASA Tech Briefs, June 2009

Topics covered include: Device for Measuring Low Flow Speed in a Duct, Measuring Thermal Conductivity of a Small Insulation Sample, Alignment Jig for the Precise Measurement of THz Radiation, Autoignition Chamber for Remote Testing of Pyrotechnic Devices, Microwave Power Combiners for Signals of Arbitrary Amplitude, Synthetic Foveal Imaging Technology, Airborne Antenna System for Minimum-Cycle-Slip GPS Reception, Improved Starting Materials for Back-Illuminated Imagers, Multi-Modulator for Bandwidth-Efficient Communication, Some Improvements in Utilization of Flash Memory Devices, GPS/MEMS IMU/Microprocessor Board for Navigation, T/R Multi-Chip MMIC Modules for 150 GHz, Pneumatic Haptic Interfaces, Device Acquires and Retains Rock or Ice Samples, Cryogenic Feedthrough Test Rig, Improved Assembly for Gas Shielding During Welding or Brazing, Two-Step Plasma Process for Cleaning Indium Bonding Bumps, Tool for Crimping Flexible Circuit Leads, Yb14MnSb11 as a High-Efficiency Thermoelectric Material, Polyimide-Foam/Aerogel Composites for Thermal Insulation, Converting CSV Files to RKSML Files, Service Management Database for DSN Equipment, Chemochromic Hydrogen Leak Detectors, Compatibility of Segments of Thermoelectric Generators, Complementary Barrier Infrared Detector, JPL Greenland Moulin Exploration Probe, Ultra-Lightweight Self-Deployable Nanocomposite Structure for Habitat Applications, and Room-Temperature Ionic Liquids for Electrochemical Capacitors.

Source record↗
NASA NTRS2006

Single-Chip T/R Module for 1.2 GHz

A single-chip CMOS-based (complementary-metal-oxide-semiconductorbased) transmit/receive (T/R) module is being developed for L-band radar systems. Previous T/R module implementations required multiple chips employing different technologies (GaAs, Si, and others) combined with off-chip transmission lines and discrete components including circulators. The new design eliminates the bulky circulator, significantly reducing the size and mass of the T/R module. Compared to multi-chip designs, the single-chip CMOS can be implemented with lower cost. These innovations enable cost-effective realization of advanced phased array and synthetic aperture radar systems that require integration of thousands of T/R modules. The circulator is a ferromagnetic device that directs the flow of the RF (radio frequency) power during transmission and reception. During transmission, the circulator delivers the transmitted power from the amplifier to the antenna, while preventing it from damaging the sensitive receiver circuitry. During reception, the circulator directs the energy from the antenna to the low-noise amplifier (LNA) while isolating the output of the power amplifier (PA). In principle, a circulator could be replaced by series transistors acting as electronic switches. However, in practice, the integration of conventional series transistors into a T/R chip introduces significant losses and noise. The prototype single-chip T/R module contains integrated transistor switches, but not connected in series; instead, they are connected in a shunt configuration with resonant circuits (see figure). The shunt/resonant circuit topology not only reduces the losses associated with conventional semiconductor switches but also provides beneficial transformation of impedances for the PA and the LNA. It provides full singlepole/ double-throw switching for the antenna, isolating the LNA from the transmitted signal and isolating the PA from the received signal. During reception, the voltage on control line RX/TX (raised bar) is high, causing the field-effect transistor (FET) switch S1 to be closed, forming a parallel resonant tank circuit L1||C1. This circuit presents high impedance to the left of the antenna, so that the received signal is coupled to the LNA. At the same time, FET switches S2 and S3 are open, so that C2 is removed from the circuit (except for a small parasitic capacitance). The combination of L2 and C3 forms a matching network that transforms the antenna impedance of 50 ohms to a higher value from the perspective of the LNA input terminal. This transformation of impedance improves LNA noise figure by increasing the received voltage delivered to the input transistor. This allows lower transconductance and therefore a smaller transistor, which makes it possible to design the CMOS LNA for low power consumption. During transmission, the voltage on control line RX/TX (raised bar) is low, causing switch S1 to be open. In this configuration, the combination of L1 and C1 transforms the antenna impedance to a lower value from the perspective of the PA. This low impedance is helpful in producing a relatively high output power compatible with the low CMOS operating potential. At the same time, switches S2 and S3 are closed, forming the parallel resonant tank circuit L2||C2. This circuit presents high impedance to the right of the antenna, directing the PA output signal to the antenna and away from the LNA. During this time, S3 presents a short circuit across the LNA input terminals to guarantee that the voltage seen by the LNA is small enough to prevent damage.

Moussessian, Alina↗