SEARCH · Search NASA

Results for “N-doping”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

SourceResearch connectionFrom yearThrough year

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 19 records

All sources NASA NTRS DOE OSTI

NASA NTRS1972

Shielded silicon gate complementary MOS integrated circuit.

An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. N-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on an oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200 C plus or minus 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous.

Lin, H. C.↗

NASA NTRS1992

Infrared Multiple-Quantum-Well Phototransistor

Proposed npn AlxGa1-xAs phototransistor incorporates multiple-quantum-well (MQW) infrared photodetector. Has n-doped contacts and is embedded between p-doped base region and n-doped collector region of transistor. Photocurrent amplified, and dark current suppressed.

Borenstain, Shmuel I.↗

NASA NTRS2004

Very High Efficiency, Miniaturized, Long-Lived Alpha Particle Power Source Using Diamond Devices for Extreme Space Environments

A power source that converts a-particle energy into electricity by coulomb collision in doped diamond films is described. Alpha particle decay from curium-244 creates electron-hole pairs by free- ing electrons and holes inside the crystal lattice in N- and P-doped diamond films. Ohmic contacts provide electrical connection to an electronic device. Due to the built-in electric field at the rectifying junction across the hT- and P-doped diamond films, the free electrons are constrained to traveling in generally one direction. This one direction then supplies electrons in a manner similar to that of a battery. The radioactive curium layer may be disposed on diamond films for even distribution of a-particle radiation. The resulting power source may be mounted on a diamond substrate that serves to insulate structures below the diamond substrate from a-particle emission. Additional insulation or isolation may be provided in order to prevent damage from a-particle collision. N-doped silicon may be used instead of N-doped diamond.

Elizabeth A Kolawa↗

NASA NTRS2011

Nano-multiplication region avalanche photodiodes and arrays

An avalanche photodiode with a nano-scale reach-through structure comprising n-doped and p-doped regions, formed on a silicon island on an insulator, so that the avalanche photodiode may be electrically isolated from other circuitry on other silicon islands on the same silicon chip as the avalanche photodiode. For some embodiments, multiplied holes generated by an avalanche reduces the electric field in the depletion region of the n-doped and p-doped regions to bring about self-quenching of the avalanche photodiode. Other embodiments are described and claimed.

Zheng, Xinyu↗

NASA NTRS2011

CMOS Imager Has Better Cross-Talk and Full-Well Performance

A complementary metal oxide/semiconductor (CMOS) image detector now undergoing development is designed to exhibit less cross-talk and greater full-well capacity than do prior CMOS image detectors of the same type. Imagers of the type in question are designed to operate from low-voltage power supplies and are fabricated by processes that yield device features having dimensions in the deep submicron range. Because of the use of low supply potentials, maximum internal electric fields and depletion widths are correspondingly limited. In turn, these limitations are responsible for increases in cross-talk and decreases in charge-handling capacities. Moreover, for small pixels, lateral depletion cannot be extended. These adverse effects are even more accentuated in a back-illuminated CMOS imager, in which photogenerated charge carriers must travel across the entire thickness of the device. The figure shows a partial cross section of the structure in the device layer of the present developmental CMOS imager. (In a practical imager, the device layer would sit atop either a heavily doped silicon substrate or a thin silicon oxide layer on a silicon substrate, not shown here.) The imager chip is divided into two areas: area C, which contains readout circuits and other electronic circuits; and area I, which contains the imaging (photodetector and photogenerated-charge-collecting) pixel structures. Areas C and I are electrically isolated from each other by means of a trench filled with silicon oxide. The electrical isolation between areas C and I makes it possible to apply different supply potentials to these areas, thereby enabling optimization of the supply potential and associated design features for each area. More specifically, metal oxide semiconductor field-effect transistors (MOSFETs) that are typically included in CMOS imagers now reside in area C and can remain unchanged from established designs and operated at supply potentials prescribed for those designs, while the dopings and the lower supply potentials in area I can be tailored to optimize imager performance. In area I, the device layer includes an n+ -doped silicon layer on which is grown an n-doped silicon layer. A p-doped silicon layer is grown on top of the n -doped layer. The total imaging device thickness is the sum of the thickness of the n+, n, and p layers. A pixel photodiode is formed between a surface n+ implant, a p implant underneath it, the aforementioned p layer, and the n and n+ layers. Adjacent to the diode is a gate for transferring photogenerated charges out of the photodiode and into a floating diffusion formed by an implanted p+ layer on an implanted n-doped region. Metal contact pads are added to the back-side for providing back-side bias.

Pain, Bedabrata↗

NASA NTRS1986

Fabrication of an X-Ray Imaging Detector

X-ray detector array yields mosaic image of object emitting 1- to 30-keV range fabricated from n-doped silicon wafer. In proposed fabrication technique, thin walls of diffused n+ dopant divide wafer into pixels of rectangular cross section, each containing central electrode of thermally migrated p-type metal. This pnn+ arrangement reduces leakage current by preventing transistor action caused by pnp structure of earlier version.

Alcorn, G. E.↗

NASA NTRS1994

Cubic GaS: A Surface Passivator For GaAs

Thin films of cubic form of gallium sulfide (GaS) formed on surfaces of gallium arsenide (GaAs) substrates via metal/organic chemical vapor deposition (MOCVD). Deposited cubic GaS, crystalline lattice matched to substrate GaAs, neutralizes electrically active defects on surfaces of both n-doped and p-doped GaAs. Enabling important GaAs-based semiconducting materials to serve as substrates for metal/insulator/semiconductor (MIS) capacitors. Cubic GaS enables fabrication of ZnSe-based blue lasers and light-emitting diodes. Because GaS is optically transparent, deposited to form window layers for such optoelectronic devices as light-emitting diodes, solar optical cells, and semiconductor lasers. Its transparency makes it useful as interconnection material in optoelectronic integrated circuits. Also useful in peeled-film technology because selectively etched from GaAs.

Hepp, Aloysius F.↗

NASA NTRS1994

Making Porous Luminescent Regions In Silicon Wafers

Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

Fathauer, Robert W.↗

NASA NTRS1995

Better Ohmic Contacts For InP Semiconductor Devices

Four design modifications enable fabrication of improved ohmic contacts on InP-based semiconductor devices. First modification consists of insertion of layer of gold phosphide between n-doped InP and metal or other overlayer of contact material. Second, includes first modification plus use of particular metal overlayer to achieve very low contact resistivities. Third, also involves deposition of Au(2)P(3) interlayer; in addition, refractory metal (W or Ta) deposited to form contact overlayer. In fourth, contact layer of Auln alloy deposited directly on InP. Improved contacts exhibit low electrical resistances and fabricated without exposing devices to destructive predeposition or postdeposition treatments.

Weizer, Victor G.↗

NASA NTRS1995

The 1200 K compressive properties of N-containing NiAl

As part of a series of experiments to understand the role of N on the strength of NiAl, a heat of NiAl was enriched with N by melting and atomization to powder in a nitrogen atmosphere. Following consolidation of the powder by hot extrusion, 1200 K compressive properties were measured in air. Within the range of strain rates examined, 10(exp -3) to 10(exp -9) s(exp -1), the strength of the N-enriched NiAl was greater than that of a simple 15 micron grain size polycrystalline, binary NiAl alloy. For the most part the overall improvement in strength is ascribed to the fine grain size of the N-doped NiAl rather than the alloy chemistry; however, the alloy displayed a complex behavior exhibiting both weakening effects as well as strengthening ones.

Whittenberger, J. Daniel↗

NASA NTRS1996

Effect of variations in the doping profiles on the properties of doped multiple quantum well avalanche photodiodes

The purpose of this study is to use both theoretical and experimental evidence to determine the impact of doping imbalance and symmetry on the physical and electrical characteristics of doped multiple quantum well avalanche photodiodes (APD). Theoretical models have been developed to calculate the electric field valence and conduction bands, capacitance-voltage (CV), and carrier concentration versus depletion depth profiles. The models showed a strong correlation between the p- and n-doping balance inside the GaAs wells and the number of depleted stages and breakdown voltage of the APD. A periodic doping imbalance in the wells has been shown to result in a gradual increase (or decrease) in the electric field profile throughout the device which gave rise to partially depleted devices at low bias. The MQW APD structures that we modeled consisted of a 1 micron top p(+)-doped (3 x 10(exp 18) cm(exp -3)) GaAs layer followed by a 1 micron region of alternating layers of GaAs (500 A) and Al(0.42)Ga(0.58)As (500 A), and a 1 micron n(+) back layer (3 x 10(exp 18) cm(exp -3)). The GaAs wells were doped with p-i-n layers placed at the center of each well. The simulation results showed that in an APD with nine doped wells, and where the 50 A p-doped layer is off by 10% (p = 1.65 x 10(exp 18) cm(exp -3), n = 1.5 x 10(exp 18) cm(exp -3)), almost half of the MQW stages were shown to be undepleted at low bias which was a result of a reduction in the electric field near the p(+) cap layer by over 50% from its value in the balanced structure. Experimental CV and IV data on similar MBE grown MQW structures have shown very similar depletion and breakdown characteristics. The models have enabled us to better interpret our experimental data and to determine both the extent of the doping imbalances in the devices as well as the overall p- or n-type doping characteristics of the structures.

Menkara, H. M.↗

NASA NTRS1995

1200 K Compressive Properties of N-Containing Nial

As part of a series of experiments to understand the role of N on the strength of NiAl, a heat of NiAl was enriched with N by melting and atomization to powder in a nitrogen atmosphere. Following consolidation of the powder by hot extrusion, 1200 K compressive properties were measured in air. Within the range of strain rates examined, 10 exp -3 to 10 exp -9/s, the strength of the N-enriched NiAl was greater than that of a simple 15 micron grain size polycrystalline, binary NiAl alloy. For the most part the overall improvement in strength is ascribed to the fine grain size of the N-doped NiAl rather than the alloy chemistry; however, the alloy displayed a complex behavior exhibiting both weakening effects as well as strengthening ones.

Whittenberger, J. D.↗

NASA NTRS1996

Microalloying Improves the Low-Cycle Fatigue Behavior of Powder-Extruded NiAl

There is considerable interest in developing new structural materials in which high use temperatures and strength, coupled with low density, are the minimum requirements. The goal for these new materials is to provide operation well beyond the working range of conventional superalloys. Of the many intermetallics under consideration, NiAl is one of the few systems that has emerged as a promising candidate for further development. This is because of a number of property advantages--including low density, high melting temperature, high thermal conductivity, and excellent environmental resistance. However, binary NiAl lacks strength and creep resistance at elevated temperatures. Also, its poor high-temperature strength results in worse-than-predicted low-cycle fatigue (LCF) lives at low strain ranges at 727 C (1341 F) because of accelerated creep damage mechanisms that result in significant intergranular cracking. One approach for improving these properties involves microalloying NiAl with either Zr or N. As an integral part of this alloy-development program at the NASA Lewis Research Center, the low-cycle fatigue behavior of Zr- and N-doped nickel aluminides produced by extrusion of prealloyed powders was investigated and compared with similarly processed binary NiAl.

Source record↗

NASA NTRS1986

Reactively-sputtered zinc semiconductor films of high conductivity for heterojunction devices

A high conductivity, n-doped semiconductor film is produced from zinc, or Zn and Cd, and group VI elements selected from Se, S and Te in a reactive magnetron sputtering system having a chamber with one or two targets, a substrate holder, means for heating the substrate holder, and an electric field for ionizing gases in the chamber. Zinc or a compound of Zn and Cd is placed in the position of one of the two targets and doping material in the position of the other of the two targets. Zn and Cd may be placed in separate targets while a dopant is placed in the third target. Another possibility is to place an alloy of Zn and dopant, or Zn, Cd and dopant in one target, thus using only one target. A flow of the inert gas is ionized and directed toward said targets, while a flow of a reactant gas consisting of hydrides of the group VI elements is directed toward a substrate on the holder. The targets are biased to attract negatively ionized inert gas. The desired stochiometry for high conductivity is achieved by controlling the temperature of the substrate, and partial pressures of the gases, and the target power and total pressure of the gases in the chamber.

Stirn, Richard J.↗

NASA NTRS2009

G(sup 4)FET Implementations of Some Logic Circuits

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Mojarradi, Mohammad↗

NASA NTRS2007

Design and Fabrication of High-Efficiency CMOS/CCD Imagers

An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the device silicon layer during micro-fabrication.

Pain, Bedabrata↗

NASA NTRS2006

Silicon-Based Optical Modulator with Ferroelectric Layer

According to a proposal, a silicon dioxide layer in a high-speed, low-power, silicon- based electro-optical modulator would be replaced by a layer of lead zirconate titanate or other ferroelectric oxide material. The purpose of this modification is to enhance the power performance and functionality of the modulator. In its unmodified form, the particular silicon- based electro-optical modulator is of an advanced design that overcomes the speed limitation of prior silicon-based electro- optical modulators. Whereas modulation frequencies of such devices had been limited to about 20 MHz, this modulator can operate at modulation frequencies as high as 1 GHz. This modulator can be characterized as a silicon-waveguide-based metal oxide/semiconductor (MOS) capacitor phase shifter in which modulation of the index of refraction in silicon is obtained by exploiting the free-charge-carrier-plasma dispersion effect. As shown in the figure, the modulator includes an n-doped crystalline silicon slab (the silicon layer of a silicon- on-insulator wafer) and a p-doped polycrystalline silicon rib with a gate oxide layer (the aforementioned silicon dioxide layer) sandwiched between them. Under accumulation conditions, the majority charge carriers in the silicon waveguide modify the index of refraction so that a phase shift is induced in the optical mode propagating in the waveguide. The advantage of using an MOS capacitor phase shifter is that it is possible to achieve high modulation speed because there are no slow carrier-generation or -recombination processes involved in the accumulation operation. The main advantage of the proposed substitution of a ferroelectric oxide layer for the silicon dioxide layer would arise from the spontaneous polarization effect of the ferroelectric layer: This spontaneous polarization would maintain accumulation conditions in the absence of applied voltage. Consequently, once the device had been switched to a given optical state, it would remain in that state, even in the absence of applied voltage (in other words, even with power turned off). A secondary advantage is that because the ferroelectric layer would have an index of refraction larger than that of silicon dioxide, there could be some reduction of optical losses attributable to fabrication of the modulator

Sheldon, Douglas↗

NASA NTRS2005

N-Type delta Doping of High-Purity Silicon Imaging Arrays

A process for n-type (electron-donor) delta doping has shown promise as a means of modifying back-illuminated image detectors made from n-doped high-purity silicon to enable them to detect high-energy photons (ultraviolet and x-rays) and low-energy charged particles (electrons and ions). This process is applicable to imaging detectors of several types, including charge-coupled devices, hybrid devices, and complementary metal oxide/semiconductor detector arrays. Delta doping is so named because its density-vs.-depth characteristic is reminiscent of the Dirac delta function (impulse function): the dopant is highly concentrated in a very thin layer. Preferably, the dopant is concentrated in one or at most two atomic layers in a crystal plane and, therefore, delta doping is also known as atomic-plane doping. The use of doping to enable detection of high-energy photons and low-energy particles was reported in several prior NASA Tech Briefs articles. As described in more detail in those articles, the main benefit afforded by delta doping of a back-illuminated silicon detector is to eliminate a "dead" layer at the back surface of the silicon wherein high-energy photons and low-energy particles are absorbed without detection. An additional benefit is that the delta-doped layer can serve as a back-side electrical contact. Delta doping of p-type silicon detectors is well established. The development of the present process addresses concerns specific to the delta doping of high-purity silicon detectors, which are typically n-type. The present process involves relatively low temperatures, is fully compatible with other processes used to fabricate the detectors, and does not entail interruption of those processes. Indeed, this process can be the last stage in the fabrication of an imaging detector that has, in all other respects, already been fully processed, including metallized. This process includes molecular-beam epitaxy (MBE) for deposition of three layers, including metallization. The success of the process depends on accurate temperature control, surface treatment, growth of high-quality crystalline silicon, and precise control of thicknesses of layers. MBE affords the necessary nanometer- scale control of the placement of atoms for delta doping. More specifically, the process consists of MBE deposition of a thin silicon buffer layer, the n-type delta doping layer, and a thin silicon cap layer. The n dopant selected for initial experiments was antimony, but other n dopants as (phosphorus or arsenic) could be used. All n-type dopants in silicon tend to surface-segregate during growth, leading to a broadened dopant-concentration- versus-depth profile. In order to keep the profile as narrow as possible, the substrate temperature is held below 300 C during deposition of the silicon cap layer onto the antimony delta layer. The deposition of silicon includes a silicon- surface-preparation step, involving H-termination, that enables the growth of high-quality crystalline silicon at the relatively low temperature with close to full electrical activation of donors in the surface layer.

Blacksberg, Jordana↗