Search NASA⌕ Search

SEARCH · Search NASA

Results for “SRAM”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 19 records
All sourcesNASA NTRSDOE OSTI
NASA NTRS1990

Alpha-particle sensitive test SRAMs

A bench-level test is being developed to evaluate memory-cell upsets in a test SRAM designed with a cell offset voltage. This offset voltage controls the critical charge needed to upset the cell. The effect is demonstrated using a specially designed 2-micron n-well CMOS 4-kb test SRAM and a Po-208 5.1-MeV 0.61-LET alpha-particle source. This test SRAM has been made sensitive to alpha particles through the use of a cell offset voltage, and this has allowed a bench-level characterization in a laboratory setting. The experimental data are linked to a alpha-particle interaction physics and to SPICE circuit simulations through the alpha-particle collection depth. The collection depth is determined by two methods and found to be about 7 micron. In addition, alpha particles that struck outside the bloated drain were able to flip the SRAM cells. This lateral charge collection was observed to be more than 6 micron.

Buehler, M. G.↗
NASA NTRS2008

Characterizing SRAM Single Event Upset in Terms of Single and Double Node Charge Collection

A well-collapse source-injection mode for SRAM SEU is demonstrated through TCAD modeling. The recovery of the SRAM s state is shown to be based upon the resistive path from the p+-sources in the SRAM to the well. Multiple cell upset patterns for direct charge collection and the well-collapse source-injection mechanisms are then predicted and compared to recent SRAM test data.

Black, J. D.↗
NASA NTRS2002

Dose measurement based on threshold shift in MOSFET arrays in commercial SRAMS

A new method using an array of MOS transistors isdescribed for measuring dose absorbed from ionizingradiation. Using the array of MOSFETs in a SRAM, a direct measurement of the number of MOS cells which change as a function of applied bias on the SRAM. Since the input and output of a SRAM used as a dosimeter is completely digital, the measurement of dose is easily accessible by a remote processing system.

SRAM dosimetry microdosimetry threshold shift↗
NASA NTRS1993

SRAM As An Array Of Energetic-Ion Detectors

Static random-access memory (SRAM) designed for use as array of energetic-ion detectors. Exploits well-known tendency of incident energetic ions to cause bit flips in cells of electronic memories. Design of ion-detector SRAM involves modifications of standard SRAM design to increase sensitivity to ions. Device fabricated by use of conventional complementary metal oxide/semiconductor (CMOS) processes. Potential uses include gas densimetry, position sensing, and measurement of cosmic-ray spectrum.

Buehler, Martin G.↗
NASA NTRS1999

SRAM Based Re-programmable FPGA for Space Applications

An SRAM (static random access memory)-based reprogrammable FPGA (field programmable gate array) is investigated for space applications. A new commercial prototype, named the RS family, was used as an example for the investigation. The device is fabricated in a 0.25 micrometers CMOS technology. Its architecture is reviewed to provide a better understanding of the impact of single event upset (SEU) on the device during operation. The SEU effect of different memories available on the device is evaluated. Heavy ion test data and SPICE simulations are used integrally to extract the threshold LET (linear energy transfer). Together with the saturation cross-section measurement from the layout, a rate prediction is done on each memory type. The SEU in the configuration SRAM is identified as the dominant failure mode and is discussed in detail. The single event transient error in combinational logic is also investigated and simulated by SPICE. SEU mitigation by hardening the memories and employing EDAC (error detection and correction) at the device level are presented. For the configuration SRAM (CSRAM) cell, the trade-off between resistor de-coupling and redundancy hardening techniques are investigated with interesting results. Preliminary heavy ion test data show no sign of SEL (single event latch-up). With regard to ionizing radiation effects, the increase in static leakage current (static I(sub CC)) measured indicates a device tolerance of approximately 50krad(Si).

Wang, J. J.↗
NASA NTRS2011

Characteristics of a Nonvolatile SRAM Memory Cell Utilizing a Ferroelectric Transistor

The SRAM cell circuit is a standard for volatile data storage. When utilizing one or more ferroelectric transistors, the hysteresis characteristics give unique properties to the SRAM circuit, providing for investigation into the development of a nonvolatile memory cell. This paper discusses various formations of the SRAM circuit, using ferroelectric transistors, n-channel and p-channel MOSFETs, and resistive loads. With varied source and supply voltages, the effects on the timing and retention characteristics are investigated, including retention times of up to 24 hours.

Mitchell, Cody↗
NASA NTRS1994

SRAM Detector Calibration

Custom proton sensitive SRAM chips are being flown on the BMDO Clementine missions and Space Technology Research Vehicle experiments. This paper describes the calibration procedure for the SRAM proton detectors and their response to the space environment.

SRAM BMDO Clementine↗
NASA NTRS1995

Depth Measurements Using Alpha Particles and Upsettable SRAMs

A custom designed SRAM was used to measure the thickness of integrated circuit over layers and the epi-layer thickness using alpha particles and a test SRAM. The over layer consists of oxide, nitride, metal, and junction regions.

upsettable SRAMs↗
NASA NTRS1986

An analytical method for predicting CMOS SRAM upsets with application to asymmetrical memory cells

An analytical method was developed to predict the heavy-ion-induced upset rate of static random access memory (SRAM) cells. The method was applied to the design of a memory with asymmetrical cells where the goal was to increase the upset rate in order to increase the number of observed upsets in a space environment. The asymmetry is achieved by increasing the drain area of selected transistors in the cell. Results from the analytical model for a space environment indicate the upset rate for the experimental asymmetrical cell (17.2 upsets/1 kbit-year) will be 4.7 times larger than the upset rate for the minimum-geometry balanced cell (3.6 upsets/1 kbit-year). The asymmetrical SRAM was designed into a test chip intended for the Combined Release and Radiation Effects Satellite (CRRES).

Buehler, Martin G.↗
NASA NTRS1993

Thin Rechargeable Batteries for CMOS SRAM Memory Protection

New rechargeable battery technology is described and compared with classical primary battery back-up of SRAM PC cards. Thin solid polymer electrolyte cells with the thickness of TSOP memory components (1 mm nominal, 1.1 mm max) and capacities of 14 mAh/sq cm can replace coin cells. The SRAM PC cards with permanently installed rechargeable cells and optional electrochromic low battery voltage indicators will free the periodic PC card user from having to 'feed' their PC cards with coin cells and will allow a quick visual check of stored cards for their battery voltage status.

Crouse, Dennis N.↗
NASA NTRS1994

Clementine RRELAX SRAM Particle Spectrometer

The Clementine RRELAX radiation monitor chip consists of a p-FET total dose monitor and a 4-kbit SRAM particle spectrometer. Eight of these chips were included in the RRELAX and used to detect the passage of the Clementine (S/C) and the innerstage adapter (ISA) through the earth's radiation belts and the 21-Feb 1994 solar flare. This is the first space flight for this 1.2 micron rad-soft custom CMOS radiation monitor. This paper emphasizes results from the SRAM particle detector which showed that it a) has a detection range of five orders of magnitude relative to the 21-Feb solar flare, b) is not affected by electrons, and c) detected microflares occurring with a 26.5 day period.

Clementine↗
NASA NTRS2006

Application of RADSAFE to Model Single Event Upset Response of a 0.25 micron CMOS SRAM

The RADSAFE simulation framework is described and applied to model Single Event Upsets (SEU) in a 0.25 micron CMOS 4Mbit Static Random Access Memory (SRAM). For this circuit, the RADSAFE approach produces trends similar to those expected from classical models, but more closely represents the physical mechanisms responsible for SEU in the SRAM circuit.

Warren, Kevin M.↗
NASA NTRS1993

Single Event Effects on Space Radiation Hardened 64K SRAMS at Room temperature

The laser threshold linear Energy transfer for single event upsetscan be estimaed, even at room temperature, for space radiation hardened 64K SRAMs. The memories where independently developed to quality for the Qualified Manufacturer's List by IBM and Honeywell. The memory was so hard that high energy heavy ions generated by the Van de Graff could not determine the SEU threshold at room temperature. Use of pulsed Laser tests would meake it possible to forgo very expensive testing at ultra-high energy accelerators.

Space Radiation 64K SRAMS↗
NASA NTRS2005

Impact of Device Scaling on Deep Sub-micron Transistor Reliability: A Study of Reliability Trends using SRAM

As microelectronics are scaled in to the deep sub-micron regime, users of advanced technology CMOS, particularly in high-reliability applications, should reassess how scaling effects impact long-term reliability. An experimental based reliability study of industrial grade SRAMs, consisting of three different technology nodes, is proposed to substantiate current acceleration models for temperature and voltage life-stress relationships. This reliability study utilizes step-stress techniques to evaluate memory technologies (0.25mum, 0.15mum, and 0.13mum) embedded in many of today's high-reliability space/aerospace applications. Two acceleration modeling approaches are presented to relate experimental FIT calculations to Mfr's qualification data.

CMOS integrated circuits↗
NASA NTRS1986

Empirical modeling of Single-Event Upset (SEU) in NMOS depletion-mode-load static RAM (SRAM) chips

A detailed experimental investigation of single-event upset (SEU) in static RAM (SRAM) chips fabricated using a family of high-performance NMOS (HMOS) depletion-mode-load process technologies, has been done. Empirical SEU models have been developed with the aid of heavy-ion data obtained with a three-stage tandem van de Graaff accelerator. The results of this work demonstrate a method by which SEU may be empirically modeled in NMOS integrated circuits.

Zoutendyk, J. A.↗
NASA NTRS1998

Verification and Quantification of Single Event Effects on High Speed SRAM in Terrestrial Environments

As integrated circuits become more sensitive to charged particles and neutrons, anomalous performance due to single event effects (SEE) is a concern and requires experimental verification and quantification. The Center for Applied Radiation Research (CARR) at Prairie View A&M University has developed experiments as a participant in the NASA ER-2 Flight Program, the APEX balloon flight program and the Student Launch Program. Other high altitude and ground level experiments of interest to DoD and commercial applications are being developed. The experiment characterizes the SEE behavior of high speed and high density SRAM's. The system includes a PC-104 computer unit, an optical drive for storage, a test board with the components under test, and a latchup detection and reset unit. The test program will continuously monitor the stored checkerboard data pattern in the SW and record errors. Since both the computer and the optical drive contain integrated circuits, they are also vulnerable to radiation effects. A latchup detection unit with discrete components will monitor the test program and reset the system when necessary. The first results will be obtained from the NASA ER-2 flights, which are now planned to take place in early 1998 from Dryden Research Center in California. The series of flights, at altitudes up to 70,000 feet, and a variety of flight profiles should yield a distribution of conditions for correlating SEES. SEE measurements will be performed from the time of aircraft power-up on the ground throughout the flight regime until systems power-off after landing.

Huff, H.↗
NASA NTRS2008

Analysis of Single-Event Latchup Cross Section in 65 nm SRAMs

Single event latchup (SEL) in a 65 nm CMOS SRAM technology is observed and sensitivity is shown to be a strong function of lateral beam orientation, angle of incidence, and temperature. The significance of these results are discussed and the foundation for a predictive model of SEL is laid out for use with the MRED tool.

Hutson, J. M.↗
NASA NTRS2006

Fault Tolerance Implementation within SRAM Based FPGA Designs based upon Single Event Upset Occurrence Rates

Emerging technology is enabling the design community to consistently expand the amount of functionality that can be implemented within Integrated Circuits (ICs). As the number of gates placed within an FPGA increases, the complexity of the design can grow exponentially. Consequently, the ability to create reliable circuits has become an incredibly difficult task. In order to ease the complexity of design completion, the commercial design community has developed a very rigid (but effective) design methodology based on synchronous circuit techniques. In order to create faster, smaller and lower power circuits, transistor geometries and core voltages have decreased. In environments that contain ionizing energy, such a combination will increase the probability of Single Event Upsets (SEUs) and will consequently affect the state space of a circuit. In order to combat the effects of radiation, the aerospace community has developed several "Hardened by Design" (fault tolerant) design schemes. This paper will address design mitigation schemes targeted for SRAM Based FPGA CMOS devices. Because some mitigation schemes may be over zealous (too much power, area, complexity, etc.. . .), the designer should be conscious that system requirements can ease the amount of mitigation necessary for acceptable operation. Therefore, various degrees of Fault Tolerance will be demonstrated along with an analysis of its effectiveness.

Berg, Melanie↗