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At least 19 records

Single-Event Effect (SEE) Survey of Advanced Reconfigurable Field Programmable Gate Arrays: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance

The NEPP Reconfigurable Field-Programmable Gate Array (FPGA) task has been charged to evaluate reconfigurable FPGA technologies for use in space. Under this task, the Xilinx single-event-immune, reconfigurable FPGA (SIRF) XQR5VFX130 device was evaluated for SEE. Additionally, the Altera Stratix-IV and SiliconBlue iCE65 were screened for single-event latchup (SEL).

Xilinx Single-Event Effects (SEE) Test Consortium↗

Single Event Effects (SEE) Testing of Embedded DSP Cores within Microsemi RTAX4000D Field Programmable Gate Array (FPGA) Devices

Motivation for this work is: (1) Accurately characterize digital signal processor (DSP) core single-event effect (SEE) behavior (2) Test DSP cores across a large frequency range and across various input conditions (3) Isolate SEE analysis to DSP cores alone (4) Interpret SEE analysis in terms of single-event upsets (SEUs) and single-event transients (SETs) (5) Provide flight missions with accurate estimate of DSP core error rates and error signatures.

Perez, Christopher E.↗

Recent Radiation Test Results for Power MOSFETs

Single-event effect (SEE) and total ionizing dose (TID) test results are presented for various hardened and commercial power metal-oxide-semiconductor field effect transistors (MOSFETs), including vertical planar, trench, superjunction, and lateral process designs.

Lauenstein, Jean-Marie↗

Single-Event Effect Report for EPC Series eGaN FETs: The Effect of Load Conditions on Destructive SEE

Recent testing of Enhanced Power Conversion (EPC) eGaN FET devices design for power use has shown that the devices are susceptible to Single-Event Effects (SEE) that degrade or destroy the device. The exact mechanism of the SEE is not known. The testing so far has been in the static condition, in the fully off condition, and with minimal load conditions. These conditions may not be worst case. This report presents the results of a study that tests some of the load conditions for SEE. The EPC2012 and EPC1012 were chosen for the test. The tests were performed the TAMU radiation effects facility in May and June of 2013.

Scheick, Leif↗

Interpreting Space-Mission LET Requirements for SEGR in Power MOSFETs

A Technology Computer Aided Design (TCAD) simulation-based method is developed to evaluate whether derating of high-energy heavy-ion accelerator test data bounds the risk for single-event gate rupture (SEGR) from much higher energy on-orbit ions for a mission linear energy transfer (LET) requirement. It is shown that a typical derating factor of 0.75 applied to a single-event effect (SEE) response curve defined by high-energy accelerator SEGR test data provides reasonable on-orbit hardness assurance, although in a high-voltage power MOSFET, it did not bound the risk of failure.

Lauenstein, J. M.↗

Diagnosis of NMOS DRAM functional performance as affected by a picosecond dye laser

A picosec pulsed dye laser beam was at selected wavelengths successfully used to simulate heavy-ion single-event effects (SEEs) in negative channel NMOS DRAMs. A DRAM was used to develop the test technique because bit-mapping capability and previous heavy-ion upset data were available. The present analysis is the first to establish such a correlation between laser and heavy-ion data for devices, such as the NMOS DRAM, where charge collection is dominated by long-range diffusion, which is controlled by carrier density at remote distances from a depletion region. In the latter case, penetration depth is an important parameter and is included in the present analysis. A single-pulse picosecond dye laser beam (1.5 microns diameter) focused onto a single cell component can upset a single memory cell; clusters of memory cell upsets (multiple errors) were observed when the laser energy was increased above the threshold energy. The multiple errors were analyzed as a function of the bias voltage and total energy of a single pulse. A diffusion model to distinguish the multiple upsets from the laser-induced charge agreed well with previously reported heavy ion data.

Kim, Q.↗

Radiation Testing and Evaluation Issues for Modern Integrated Circuits

Abstract. Changes in modern integrated circuit (IC) technologies have modified the way we approach and conduct radiation tolerance and testing of electronics. These changes include scaling of geometries, new materials, new packaging technologies, and overall speed and device complexity challenges. In this short course section, we will identify and discuss these issues as they impact radiation testing, modeling, and effects mitigation of modern integrated circuits. The focus will be on CMOS-based technologies, however, other high performance technologies will be discussed where appropriate. The effects of concern will be: Single-Event Effects (SEE) and steady state total ionizing dose (TID) IC response. However, due to the growing use of opto-electronics in space systems issues concerning displacement damage testing will also be considered. This short course section is not intended to provide detailed "how-to-test" information, but simply provide a snapshot of current challenges and some of the approaches being considered.

LaBel, Kenneth A.↗

Initial SEE Testing of Maestro

We have reported on initial SEE sensitivity of the full 49-core Maestro device. Supporting the low-level structures and qualitative system observation goals of phase 1 of testing. Observed sensitivities found to be consistent with Boeing predictions. Highlighted by the L1 data cache sensitivity which drives the rates on the current Maestro device. Presented details to the hardware and software setups that show where the limitations - highlighting future work. Key future work includes testing with memory and IO ports.

cache sensitivity↗

SEE and TID of emerging non-volatile memories

We report on the SEE and TID tests of higher density flash memories. Stand-by currents and full functional tests were used to characterize the response of radiation effects.

single-event upset non-volatile memories↗

Guideline for ground radiation testing of microprocessors in the space radiation environment

The goal of this work is to develop a guideline that is applicable to processors that are potentially useful in space. Thus, the guideline does not consider very high performance processors that are intended for server or high-performance applications where very large amounts of power are tolerated to gain performance because it would be impractical to use such high-power devices in typical space applications. This guide is intended to support insertion of these microprocessors into spaceflight applications and to recommend ground test protocols. The first guideline principle that should be followed is a serious concurrent engineering approach for down selecting space-qualified microprocessors. This requires that the design engineer seek the support of a radiation effects expert who understands total ionizing dose (TID) and single-event effects (SEEs) issues for microprocessors as applied to the system in question.

Irom, Farokh↗

What Reliability Engineers Should Know about Space Radiation Effects

Space radiation in space systems present unique failure modes and considerations for reliability engineers. Radiation effects is not a one size fits all field. Threat conditions that must be addressed for a given mission depend on the mission orbital profile, the technologies of parts used in critical functions and on application considerations, such as supply voltages, temperature, duty cycle, and redundancy. In general, the threats that must be addressed are of two types-the cumulative degradation mechanisms of total ionizing dose (TID) and displacement damage (DD). and the prompt responses of components to ionizing particles (protons and heavy ions) falling under the heading of single-event effects. Generally degradation mechanisms behave like wear-out mechanisms on any active components in a system: Total Ionizing Dose (TID) and Displacement Damage: (1) TID affects all active devices over time. Devices can fail either because of parametric shifts that prevent the device from fulfilling its application or due to device failures where the device stops functioning altogether. Since this failure mode varies from part to part and lot to lot, lot qualification testing with sufficient statistics is vital. Displacement damage failures are caused by the displacement of semiconductor atoms from their lattice positions. As with TID, failures can be either parametric or catastrophic, although parametric degradation is more common for displacement damage. Lot testing is critical not just to assure proper device fi.mctionality throughout the mission. It can also suggest remediation strategies when a device fails. This paper will look at these effects on a variety of devices in a variety of applications. This paper will look at these effects on a variety of devices in a variety of applications. (2) On the NEAR mission a functional failure was traced to a PIN diode failure caused by TID induced high leakage currents. NEAR was able to recover from the failure by reversing the current of a nearby Thermal Electric Cooler (turning the TEC into a heater). The elevated temperature caused the PIN diode to anneal and the device to recover. It was by lot qualification testing that NEAR knew the diode would recover when annealed. This paper will look at these effects on a variety of devices in a variety of applications. Single Event Effects (SEE): (1) In contrast to TID and displacement damage, Single Event Effects (SEE) resemble random failures. SEE modes can range from changes in device logic (single-event upset, or SEU). temporary disturbances (single-event transient) to catastrophic effects such as the destructive SEE modes, single-event latchup (SEL). single-event gate rupture (SEGR) and single-event burnout (SEB) (2) The consequences of nondestructive SEE modes such as SEU and SET depend critically on their application--and may range from trivial nuisance errors to catastrophic loss of mission. It is critical not just to ensure that potentially susceptible devices are well characterized for their susceptibility, but also to work with design engineers to understand the implications of each error mode. -For destructive SEE, the predominant risk mitigation strategy is to avoid susceptible parts, or if that is not possible. to avoid conditions under which the part may be susceptible. Destructive SEE mechanisms are often not well understood, and testing is slow and expensive, making rate prediction very challenging. (3) Because the consequences of radiation failure and degradation modes depend so critically on the application as well as the component technology, it is essential that radiation, component. design and system engineers work togetherpreferably starting early in the program to ensure critical applications are addressed in time to optimize the probability of mission success.

DiBari, Rebecca↗

Localized Triple Modular Redundancy vs. Distributed Triple Modular Redundancy on a ProASIC3E Reprogrammable FPGA

Field programmable gate arrays (FPGA) are used in every space application. Currently, most space flight applications use radiation hardened (RH) FPGAs, which are very expensive. There is a desire to use cheaper, commercial off the shelf reprogrammable FPGAs, which are more susceptible to radiation effects known as single-event effects (SEE). The RH parts have SEE and total ionizing dose (TID) hardened elements pre-integrated into the part. This means that the designer does not need to implement any hardening techniques while configuring the device. The COTS parts on the other hand must be mitigated by design in order to insure any form of mitigation. The design techniques this project examines concern the use of localized triple modular redundancy (LTMR) and distributed triple modular redundancy (DTMR). LTMR triples every flip flop in the device architecture while DTMR triples everything except for the global routes (clocks, resets, and enables). The testing was performed on a ProASIC3E FPGA at the Texas A&M cyclotron facility. Two design architectures were used: shift registers and counters, both with LTMR and DTMR mitigation techniques. The test results prove that DTMR is more effective at reducing SEE than LTMR. We also determined that there was not a significant difference between the use of shift registers and counters for test purposes. More testing is required to obtain additional linear energy transfer values for each architecture and mitigation technique in order to determine the most cost-effective method of SEE mitigation.

McGuffey, Alex↗

Radiation Tests of Highly Scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories - Update 2012

The space radiation environment poses a certain risk to all electronic components on Earth-orbiting and planetary mission spacecraft. In recent years, there has been increased interest in the use of high-density, commercial, nonvolatile flash memories in space because of ever-increasing data volumes and strict power requirements. They are used in a wide variety of spacecraft subsystems. At one end of the spectrum, flash memories are used to store small amounts of mission-critical data such as boot code or configuration files and, at the other end, they are used to construct multi-gigabyte data recorders that record mission science data. This report examines single-event effect (SEE) and total ionizing dose (TID) response in single-level cell (SLC) 32-Gb, multi-level cell (MLC) 64-Gb, and Triple-level (TLC) 64-Gb NAND flash memories manufactured by Micron Technology with feature size of 25 nm.

Irom, Farokh↗

Radiation tests of highly scaled, high-density, commercial, nonvolatile NAND flash memories— update 2012

The space radiation environment poses a certain risk to all electronic components on Earth-orbiting and planetary mission spacecraft. In recent years, there has been increased interest in the use of high-density, commercial, nonvolatile flash memories in space because of ever-increasing data volumes and strict power requirements. They are used in a wide variety of spacecraft subsystems. At one end of the spectrum, flash memories are used to store small amounts of mission-critical data such as boot code or configuration files and, at the other end, they are used to construct multi-gigabyte data recorders that record mission science data. This report examines single-event effect (SEE) and total ionizing dose (TID) response in single-level cell (SLC) 32-Gb, multi-level cell (MLC) 64-Gb, and Triple-level (TLC) 64-Gb NAND flash memories manufactured by Micron Technology with feature size of 25 nm.

Allen, Gregory R.↗

Tradeoffs in Flight Design Upset Mitigation in State of the Art FPGAs: Hardened by Design vs. Design Level Hardening

This presentation compares and contrasts the effectiveness and the system/designer impacts of the two main approaches to upset hardening: the Actel approach (RTSX-S and RTAX-S) of low-level (inside each flip-flop) triplication and the Xilinx approach (Virtex and Virtex2) of design-level triplication of both functional blocks and voters. The effectiveness of these approaches is compared using measurements made in conjunction with each of the FPGAs' manufacturer: for Actel, published data [1] and for Xilinx, recent results from the Xilinx SEE Test Consortium (note that the author is an active and founding member). The impacts involve Actel advantages in the areas of transistor-utilization efficiency and minimizing designer involvement in the triplication while the Xilinx advantages relate to the ability to custom tailor upset hardness and the flexibility of re-configurability. Additionally, there are currently clear Xilinx advantages in available features such as the number of I/O's, logic cells, and RAM blocks as well as speed. However, the advantage of the Actel anti-fuses for configuration over the Xilinx SRAM cells is that the latter need additional functionality and external circuitry (PROMs and, at least a watchdog timer) for configuration and configuration scrubbing. Further, although effectively mitigated if done correctly, the proton upset-ability of the Xilinx FPGAs is a concern in severe proton-rich environments. Ultimately, both manufacturers' upset hardening is limited by SEFI (single-event functional interrupt) rates where it appears the Actel results are better although the Xilinx Virtex2-family result of about one SEFI in 65 device-years in solar-min GCR (the more intense part of the galactic cosmic-ray background) should be acceptable to most missions

radiation effects↗

Single-Event Effects Ground Testing and On-Orbit Rate Prediction Methods: The Past, Present and Future

Over the past 27 years, or so, increased concern over single event effects in spacecraft systems has resulted in research, development and engineering activities centered around a better understanding of the space radiation environment, single event effects predictive methods, ground test protocols, and test facility developments. This research has led to fairly well developed methods for assessing the impact of the space radiation environment on systems that contain SEE sensitive devices and the development of mitigation strategies either at the system or device level.

Reed, Robert A.↗

Single-Event Effect Testing of the Cree C4D40120D Commercial 1200V Silicon Carbide Schottky Diode

This study was undertaken to determine the single event effect (SEE) susceptibility of the commercial silicon carbide 1200V Schottky diode manufactured by Cree, Inc. Heavy-ion testing was conducted at the Texas A&M University Cyclotron Single Event Effects Test Facility (TAMU). Its purpose was to evaluate this device as a candidate for use in the Solar-Electric Propulsion flight project.

silicon carbide (SiC)↗