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Pinhole Formation in Poly-Si/SiOx Passivating Contacts on Si(111)-Oriented Textures

Poly-Si/SiOx passivating contacts were grown on inverted pyramid and random pyramid textured wafers to investigate the hypothesis that pinhole formation is most susceptible at the valleys and edges of a textured surface. Tetramethylammonium hydroxide (TMAH) etching and electron beam induced current (EBIC) were used to assess pinhole formation and charge-carrier transport. Scanning electron microscopy revealed that TMAH etching can expose pinhole locations on textured surfaces. We show that pinholes may preferentially form at the vertices of inverted pyramids. Our TMAH and EBIC analyses on random pyramids show no preferential oxide breakup at the pyramid valleys.

41 EE - Solar Energy Technologies Office (EE-4S)↗

Self‐Assembled Monolayer Templating for Engineered Nanopinholes in Passivated Contact Solar Cells

We present a novel self-assembled monolayer (SAM)-based technique to make nanopinhole-enabled passivated contacts on silicon solar cells by tuning the SAM coverage area and etch selectivity. We deposit trimethyl-silyl Si(CH 3 ) 3 groups using hexamethyldisilazane (HMDS) as the precursor over passivating dielectric layers and their stacks (SiO 2 , SiN x , SiO 2 /SiN x ) and interrupt the HMDS attachment chemistry shortly before a full monolayer is formed on its surface. Subsequent etching in dilute HF produces pinholes through the dielectric layers due to the higher etch resistance of the SAM to HF etching. The pinhole areal density (10 4 –10 8 /cm 2 ) and size (10–1000 nm) can be tuned both by duration of HMDS attachment and HF etch time. Pinholes were characterized by atomic force microscopy, tetramethylammonium hydroxide (TMAH) selective etch, and Ag decoration by electroless plating. Polysilicon (poly-Si) passivated contacts enabled by pinholes were formed by subsequent deposition of doped amorphous silicon (a-Si:H) followed by thermal crystallization and dopant drive-in. At optimal areal pinhole density ≈10 7 /cm 2 , contacts exhibit both passivation and carrier transport via pinholes as evidenced by electron beam induced current, transmission line measurements, and carrier lifetime measurements. Solar cells based with these pinhole contacts show V oc = 723 mV and FF = 80.3%. The remaining SAM layer does not affect device performance.

14 SOLAR ENERGY↗

Vertical Etching of Scandium Aluminum Nitride Thin Films Using TMAH Solution

A wide bandgap, an enhanced piezoelectric coefficient, and low dielectric permittivity are some of the outstanding properties that have made Sc x Al 1-x N a promising material in numerous MEMS and optoelectronics applications. One of the substantial challenges of fabricating Sc x Al 1-x N devices is its difficulty in etching, specifically with higher scandium concentration. In this work, we have developed an experimental approach with high temperature annealing followed by a wet etching process using tetramethyl ammonium hydroxide (TMAH), which maintains etching uniformity across various Sc compositions. The experimental results of etching approximately 730 nm of Sc x Al 1-x N (x = 0.125, 0.20, 0.40) thin films show that the etch rate decreases with increasing scandium content. Nevertheless, sidewall verticality of 85°~90° (±0.2°) was maintained for all Sc compositions. Based on these experimental outcomes, it is anticipated that this etching procedure will be advantageous in the fabrication of acoustic, photonic, and piezoelectric devices.

36 MATERIALS SCIENCE↗

Multi-Functional, Micro Electromechanical Silicon Carbide Accelerometer

A method of bulk manufacturing SiC sensors is disclosed and claimed. Materials other than SiC may be used as the substrate material. Sensors requiring that the SiC substrate be pierced are also disclosed and claimed. A process flow reversal is employed whereby the metallization is applied first before the recesses are etched into or through the wafer. Aluminum is deposited on the entire planar surface of the metallization. Photoresist is spun onto the substantially planar surface of the Aluminum which is subsequently masked (and developed and removed). Unwanted Aluminum is etched with aqueous TMAH and subsequently the metallization is dry etched. Photoresist is spun onto the still substantially planar surface of Aluminum and oxide and then masked (and developed and removed) leaving the unimidized photoresist behind. Next, ITO is applied over the still substantially planar surface of Aluminum, oxide and unimidized photoresist. Unimidized and exposed photoresist and ITO directly above it are removed with Acetone. Next, deep reactive ion etching attacks exposed oxide not protected by ITO. Finally, hot phosphoric acid removes the Al and ITO enabling wires to connect with the metallization. The back side of the SiS wafer may be also etched.

Robert S Okojie↗

Multi-functional micro electromechanical devices and method of bulk manufacturing same

A method of bulk manufacturing SiC sensors is disclosed and claimed. Materials other than SiC may be used as the substrate material. Sensors requiring that the SiC substrate be pierced are also disclosed and claimed. A process flow reversal is employed whereby the metallization is applied first before the recesses are etched into or through the wafer. Aluminum is deposited on the entire planar surface of the metallization. Photoresist is spun onto the substantially planar surface of the Aluminum which is subsequently masked (and developed and removed). Unwanted Aluminum is etched with aqueous TMAH and subsequently the metallization is dry etched. Photoresist is spun onto the still substantially planar surface of Aluminum and oxide and then masked (and developed and removed) leaving the unimidized photoresist behind. Next, ITO is applied over the still substantially planar surface of Aluminum, oxide and unimidized photoresist. Unimidized and exposed photoresist and ITO directly above it are removed with Acetone. Next, deep reactive ion etching attacks exposed oxide not protected by ITO. Finally, hot phosphoric acid removes the Al and ITO enabling wires to connect with the metallization. The back side of the SiC wafer may be also be etched.

Okojie, Robert S.↗

Self Assembled Monolayers for Passivated Contacts

Passivated contacts mitigate defects typically encountered due metallization of solar cells. We deposit amorphous silicon (a-Si:H) on an oxidized silicon wafer via PECVD and anneal at high temperature to crystallize into polysilicon passivated contact. One drawback is the absorption of the polysilicon between grid fingers, so removal of this material is desirable to maximize Jsc. Alternatively, interdigitated back contact cells rely on a gap between n- and p- fingers, which is commonly etched to ensure electronic isolation. We utilize a self assembled monolayer (SAM) using hexamethyldisilazane (HMDS) as a precursor to pattern and etch amorphous silicon (a-Si:H) and polysilicon without the need for photoresist. Ultraviolet light exposure oxidizes the HMDS by photocleaving the organic groups [1] of the SAM leaving a patterned SiO2. Directly soaking this in TMAH will eventually etch the SAM and the silicon, where the SiO2 serves as an etch mask. Inversely, a dilute HF dip selectively etches this SiO2 and the SAM remains. A subsequent soak in TMAH selectively etches the underlying silicon, where the SAM serves as an etch mask. Importantly, we find that the SAM can remain intact for metallization, where we measure 10 mO-cm2 specific contact resistivity on n-type polysilicon.

passivation↗

Mitigation of shunt in poly -Si/SiO$_{x}$ passivated interdigitated back contact monocrystalline Si solar cells by self-aligned etching between doped fingers

Polycrystalline silicon on silicon oxide (poly-Si/SiO x ) passivating contacts can be used for ultra-high-efficiency interdigitated back contact (IBC) monocrystalline silicon solar cells. We evaluate the use of intrinsic poly-Si for the region that isolates the p- and n-type fingers at the back side of IBC devices. To mitigate shunt across the isolation region between the doped p- and n-type fingers, we demonstrate self-aligned subtractive processing by etching the poly-Si in the isolation region using SF6 plasma followed by etching in a tetramethylammonium hydroxide (TMAH) solution. After removal of the poly-Si, the isolation region was passivated with SiN x and Al 2 O 3 , which resulted in an 11.7% increase in the fill factor in a 19.8% efficient device. Furthermore, we evaluate the limitations of this device through Suns-V oc analysis and simulations using SunSolve and Quokka3 solar cell simulation software. Through Quokka3, we show that the most significant efficiency losses come from junction recombination current (J 02 ) in the isolation region between doped fingers. We predict that the cell efficiency can be most improved with reduced J 02 through better isolation of heavily doped fingers by etching the isolation region deeper into the bulk or through enhanced surface chemical passivation in this region.

14 SOLAR ENERGY↗

Wafer-Level Membrane-Transfer Process for Fabricating MEMS

A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

Yang, Eui-Hyeok↗

Pinhole‐Free Ultrathin Silicon Oxide Layer by Ozone‐Dissolved Deionized Water

The pinhole‐free silicon oxide (SiO x ) layer grown using dissolved ozone in deionized water (DI‐O 3 ) is demonstrated. An ultrathin SiO x layer of thickness 1.53 nm ± 1.5% is grown on silicon wafer using 7 ppm DI‐O 3 . A four‐step methodology, including 25 wt% aq. tetramethylammonium hydroxide (TMAH) solution at 80 °C, is employed to magnify the pinhole signatures in the underlying silicon and visualized with dark‐field optical microscopy (DFOM) and scanning electron microscopy (SEM). The DFOM images show spots on the surface of wafer that originate from airborne particles, contamination, etc. SEM images reveal the absence of etch pits in silicon even after etching of SiO x /silicon in TMAH for 300 s. The minority carrier lifetime and interface states density in AlO x ‐capped SiO x /Si structure are ≥2 ms at carrier density of 1 × 10 15 cm −3 and less than 2 × 10 11 cm −2 eV −1 , respectively.

42 ENGINEERING↗

Restored Passivation after Complete Removal of Front Poly-Si Between the Grid in Poly-Si/SiO2 Front/Back Cells

This work explores the use of wet chemical etching to completely remove the front poly-Si layer between grid lines of a front/back poly-Si/SiO2 passivated contact device. The purpose of the work is to provide excellent passivation under the metal grid, but to also maximize Jsc by eliminating optical absorption in the front poly-Si. We show that after a high temperature anneal to distribute carriers in the poly-Si/SiO2/c-Si interface all of the poly-Si can be removed selectively with TMAH, using the SiO2 as an etch-stop layer. The etched surface can be repassivated back to its original level with the addition of a SiNx/Al2O3 stack grown on the preserved tunnelling oxide layer followed by a short forming gas anneal. Using symmetric 100 - 200 nm intrinsically doped poly-Si/SiO2 on textured n-type wafer templates we show absolute device efficiency enhancement from 15% to 21% by increasing the Jsc by 12 mA/cm2 after removing the front poly-Si and repassivating while effectively preserving the Voc, and FF of the device. IQE values are similar to PERC devices in the short wavelength range.

etching↗

Effective Dielectric Passivation Scheme in Area-Selective Front/Back Poly-Si/SiOx Passivating Contact Solar Cells

Despite the high efficiencies reached by heavily doped poly-Si/SiO x passivating contact solar cells, challenges like the high front parasitic absorption still limit their performance. Previously, we showed a wet etching technique using self-aligned metal grids to remove the front poly-Si in the non-metallized region. Here, we focus on the effective dielectric passivation on this tunneling oxide/n + in-diffused region. The effect of poly-Si thickness was studied to balance between the passivation quality and the current gain. We then compared various dielectric passivation schemes using SiN x , Al 2 O 3 , and stacks thereof via injection-level dependent lifetime and the transfer length method. We demonstrate a SiN x /Al 2 O 3 stack yielded the best passivation performance within device process limitation and obtained an improved front/back poly-Si/SiO x passivating contact device, with a short circuit current density of 41.8 mA/cm 2 and an efficiency of 21.8%.

anisotropic wet etching↗

In Situ Analysis of Electron-Induced Chemical Transformations in Vapor-Phase-Synthesized Al-Based Inorganic–Organic Hybrid Thin Films for EUV Resist Platform

The rapid advancement and stringent requirements of extreme ultraviolet (EUV) lithography technology necessitate the development of advanced photoresist systems for next-generation microelectronics. Recent studies have demonstrated that inorganic-based hybrid photoresists offer notable improvements in EUV sensitivity, etch resistance, and greater insusceptibility to pattern collapse compared to their purely organic counterparts. However, variations in the synthesis/coating approaches and chemistry of inorganic–organic photoresists can result in distinct exposure mechanisms. In this work, an Al-based hybrid thin film resist system synthesized via molecular (atomic) layer deposition (MLD or MALD) is explored, focusing on its electron-beam and EUV patterning mechanisms. The Al-based hybrid thin films are deposited using trimethylaluminum (TMA) and the organic precursor hydroquinone, exhibiting a saturated growth rate within the temperature range of 150–200°C. In diluted tetramethylammonium hydroxide (TMAH)-based developer solutions, the electron-irradiated Al-based hybrid thin film system behaves as a negative tone resist, achieving a sensitivity of 10.4 mC/cm 2 at 0.1 kV electron beam lithography (EBL). Chemical changes induced by electron exposure are also analyzed in this study using X-ray photoelectron spectroscopy (XPS), Raman spectroscopy, and a unique infrared spectroscopy setup, revealing the potential cross-linking pathways. To further correlate the electron-induced chemical transformations with those mediated by EUV irradiations, a combination of X-ray photoemission electron microscopy/low-energy electron microscopy (XPEEM/LEEM) system is also employed. In conclusion, this study provides critical insights into the mechanisms underlying solubility switching and contributes to the design of advanced resist materials for EUV lithography.

36 MATERIALS SCIENCE↗