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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Impact of 12-nm FinFET Technology Variations on TID Effects: A Comparative Study of GF 12LP and 12LP+ at the Transistor Level

Here, this article presents a comparative analysis of total ionizing dose (TID) response in GlobalFoundries’ (GF) 12 low-power (LP) and 12LP+12-nm bulk fin field effect transistor (FinFET) technologies using 10-keV X-rays. Our findings show that 12LP+ n-type transistors demonstrate higher sensitivity to TID degradation of the off-state leakage drain current compared to 12LP. Data indicate that for both 12LP and 12LP+, transistors with higher threshold voltages (VTs) exhibit lower off-state drain-source leakage postirradiation compared to transistors with lower VTs. Data consistently show that transistors with fewer fins per transistor show superior TID tolerance, in both 12LP and 12LP+ technologies. Lower VT transistors in both technologies display similar preirradiation leakage currents. On the other hand, higher VT transistors in 12LP+ show lower preirradiation leakage currents than those in 12LP, highlighting that the front-end-of-line of 12LP+ technology has been modified compared to 12LP. p-type devices in 12LP+ presented negligible degradation. Larger TID sensitivity in 12LP+ might be attributed to the implementation of dual-metal gate work functions, reduced halo doping, deeper source/drain (S/D) doping profiles, and/or 12LP+ having narrower fins compared to 12LP.

Dual-metal gate work functions↗
DOE OSTI2026

Efficient and Robust p-Type Transistor Based on Ultrawide-Bandgap Semiconductor

The p-type transistor is an indispensable component of semiconductor technology, enabling a complementary operation with n-channel transistors for computation, storage, and communication. Achieving both high robustness and high efficiency is highly desirable but challenging for p-type transistors due to the limited semiconductors with reliable hole transport and their high activation energies. Here, in this study, we achieved a robust yet efficient p-type transistor by heterogeneously integrating an ultrawide-bandgap semiconductor and a high-κ dielectric layer through van der Waals integration. The p-type transistor employs a two-dimensional hole channel on hydrogenated diamond (bandgap 5.6 eV) combined with a high-κ (30.5) SrTiO 3 perovskite membrane. At room temperature, the transistor exhibits stable operation with a high on-current (∼200 mA/mm), low subthreshold swing (70 mV/dec), high hole mobility (566 cm 2 /(V·s) to 572 cm 2 /(V·s)), and high on–off ratio (∼10 9 ). Furthermore, tuning the annealing temperature allows operation in either enhancement or depletion mode. The robust p-type transistor with high efficiency holds great potential for future power electronics, ultraviolet (UV) optoelectronics, and harsh-environment electronic applications.

high-κ membrane↗
DOE OSTI2024

Reducing the Barrier Height in Organic Transistors

Abstract Reducing the Schottky barrier height and Fermi level de‐pinning in metal‐organic semiconductor contacts are crucial for enhancing the performance of organic transistors. The reduction of the Schottky barrier height in bottom‐contact top‐gate organic transistors is demonstrated by adding 1 nm thick atomic layer deposited Al 2 O 3 on the source and drain contacts. By using two different donor‐acceptor copolymers, both p‐ and n‐ type transistors are investigated. Temperature‐dependent current–voltage measurements from non‐treated, self‐assembled monolayer treated, and Al 2 O 3 treated Au source‐drain contact field‐effect transistors with varying channel lengths are carried out. The drain current versus drain voltage near zero gate voltage, which may be described by the thermionic emission model at temperatures above 150 K, allows the estimation of the Schottky barrier height ( φ B ). The Al 2 O 3 contact‐treated transistors show more than 40% lower φ B compared with the non‐treated contacts in the p ‐type transistor. Similarly, an isoindigo‐based transistor, with n ‐type transport, shows a reduction in φ B with Al 2 O 3 treated contacts suggesting that such ultrathin oxide layers provide a universal method for reducing the barrier height.

Ghobadi, Arash↗
DOE OSTI2026

Gate-All-Around Nanowire Field-Effect Transistors: A Historical Perspective

The development of transistor architectures, evolving from 2D planar metal-oxide-semiconductor field-effect transistors (MOSFETs) to FinFETs and then to gate-all-around nanowire (GAANW) FETs, plays a crucial role in downscaling technology nodes in the semiconductor industry. This perspective reviews the concept of MOSFETs and summarizes this historical development with particular emphasis on GAANW transistors due to their importance in next-generation technology for nodes below 3 nm. Specifically, the concept of GAANW transistors and their advantages over planar and FinFET devices for further scaling are presented, along with a discussion of their transition from early conceptual ideas to laboratory demonstrations and, ultimately, industrial adoption. Furthermore, potential solutions, such as complementary FETs (CFETs) and 2D semiconductor-based FETs, and their associated challenges for the future generation, known as the Angstrom Era, are discussed in a technological roadmap. In conclusion, this perspective may inspire both industry and academia in future research directions for realizing the Angstrom Era.

gate-all-around transistors↗
DOE OSTI2025

Mobility and threshold voltage extraction in transistors with gate-voltage-dependent contact resistance

The mobility of emerging (e.g., two-dimensional, oxide, organic) semiconductors is commonly estimated from transistor current-voltage measurements. However, such devices often experience contact gating, i.e., electric fields from the gate modulate the contact resistance during measurements, which can lead conventional extraction techniques to estimate mobility incorrectly even by a factor >2. Although this error can be minimized by measuring transistors at high gate-source bias |V gs |, this regime is often inaccessible in emerging devices that suffer from high contact resistance or early gate dielectric breakdown. Here, we propose a method of extracting mobility in transistors with gate-dependent contact resistance that does not require operation at high |V gs |, enabling accurate mobility extraction even in emerging transistors with strong contact gating. Our approach relies on updating the transfer length method (TLM) and can achieve <10% error even in regimes where conventional techniques overestimate mobility by >2×

36 MATERIALS SCIENCE↗
DOE OSTI2024

Investigating the Effects of Individual Neutron-Induced Defects in Bipolar Junction Transistors

Here, this study investigates neutron-induced displacement damage in Bipolar Junction Transistors (BJTs) using TCAD models informed by Deep-Level-Transient-Spectroscopy (DLTS) data. These models are calibrated and validated against experimental measurements performed at various neutron fluences. Both npn and pnp transistor configurations are studied to analyze the effects of individual traps on carrier recombination and base leakage currents. In npn transistors, deep traps (0.42 eV from the conduction band) dominate at low voltages, while shallow traps (0.17 eV from the conduction band) become prominent at higher voltages. Conversely, pnp transistors have base leakage current predominantly due to deep-level traps. The study observes a notable trend in trap density versus fluence, characterized by a linear relationship on a log-log scale. These insights into defect evolution under radiation conditions are crucial for optimizing semiconductor device reliability and performance in radiation-prone environments.

42 ENGINEERING↗
DOE OSTI2025

2 kV Al 0.64 Ga 0.36 N-channel high electron mobility transistors with passivation and field plates

Abstract High voltage (∼2 kV) Al 0.64 Ga 0.36 N-channel high electron mobility transistors were fabricated with an on-resistance of ∼75 Ω. mm (∼21 mΩ. cm 2 ). Two field plates of variable dimensions were utilized to optimize the breakdown voltage. The breakdown voltage reached >3 kV (tool limit) before passivation however it reduced to ∼2 kV after Si 3 N 4 surface passivation and field plate deposition. The breakdown voltage and on-resistance demonstrated a strong linear correlation in a scattered plot of ∼50 measured transistors. The fabricated transistors were electrically characterized and benchmarked against the state-of-the-art high-voltage (> 1 kV) Al-rich (>40%) AlGaN-channel transistors in breakdown voltage and on-resistance, indicating significant progress.

Alam, Md Tahmidul (ORCID:000900086556839X)↗
DOE OSTI2025

Emulation of Synaptic Plasticity in WO 3 ‐Based Ion‐Gated Transistors

Neuromorphic systems, inspired by the human brain, promise significant advancements in computational efficiency and power consumption by integrating processing and memory functions, thereby addressing the von Neumann bottleneck. This paper explores the synaptic plasticity of a WO3-based ion-gated transistor (IGT) in [EMIM][TFSI] and a 0.1 mol L −1 LiTFSI in [EMIM][TFSI] for neuromorphic computing applications. Cyclic voltammetry (CV), transistor characteristics, and atomic force microscopy (AFM) force–distance (FD) profiling analyses reveal that Li + brings about ion intercalation, together with higher mobility and conductance, and slower response time (τ). WO 3 IGTs exhibit spike amplitude-dependent plasticity (SADP), spike number-dependent plasticity (SNDP), spike duration-dependent plasticity (SDDP), frequency-dependent plasticity (FDP), and paired-pulse facilitation (PPF), which are all crucial for mimicking biological synaptic functions and understanding how to achieve different types of plasticity in the same IGT. The findings underscore the importance of selecting the appropriate ionic medium to optimize the performance of synaptic transistors, enabling the development of neuromorphic systems capable of adaptive learning and real-time processing, which are essential for applications in artificial intelligence (AI).

36 MATERIALS SCIENCE↗
DOE OSTI2026

Enhancing mobility and interface state engineering via UV-ozone treatment in BEOL-compatible ultrathin TiO 2 transistors

It has emerged as a potential candidate to improve the performance of monolithic-three-dimensional (M3D) integration of fused logic and memories through low-temperature in situ synthesis of high-performance metal–oxide–semiconductor (MOS) transistors. Here, we report the demonstration of the BEOL-compatible low thermal budget (350 °C) fabrication process of ultrathin-TiO2 transistors by the combination of RTA and UV-ozone treatment (RTA-UVOz). UV–ozone (UVOz) treatment of TiO2 anatase films significantly enhances stability, boosting ION current and field effect mobility (μ FE ) by two times of magnitude in TiO2 TFTs. UV ozone treatment helps to eliminate pre-existing oxygen vacancies and carbon contamination on TiO2 channels even at low temperature (100 °C), resulting in high-quality channel/dielectric interfaces with low interface states (D it ). During UVOz treatment, oxygen species (O x ) passivate the oxygen vacancies ($V$$^{2+}_{o}$), and hence low concentration of $V$$^{2+}_{o}$ would be left for ionization/de-ionization under PBS/NBS, leading to improved bias stress stability. Furthermore, the TiO 2 TFTs with thin ZrO 2 gate dielectric exhibited excellent performance including a lower subthreshold swing (SS) of 98 mV/dec with high drive I ON current ∼ 4.5 μA/μm, a high I ON /I OFF > 10 9 , and mobility μFE of 7 cm 2 /V-s under a battery powered voltage of 1 V. UV–ozone treatment enables high-performance, CMOS-compatible TiO 2 transistors with a low thermal budget, ideal for next-generation flexible, energy-efficient electronics.

BEOL↗
DOE OSTI2025

Thermally Stable Ruthenium Contact for Robust p‑Type Tellurium Transistors

Tellurium (Te) is attractive for p-channel transistors due to its high hole mobility. Despite having a low thermal budget suitable for back-end-of-line (BEOL) monolithic integration, the practical realization of Te transistors is hindered by its thermal stability. In this work, we investigate thermal stability for Te thin films grown via scalable thermal evaporation. Our findings identify ruthenium as a more thermally stable contact for p-type Te transistors, capable of withstanding temperatures up to 250 °C. Ruthenium exhibits significantly lower diffusivity in Te compared to other contact metals commonly used such as nickel and palladium. Using the transfer-length method, we measured a contact resistance of 1.25 kΩ·μm at the ruthenium-tellurium interface. Additionally, the incorporation of high-κ ZrO2 encapsulation not only suppresses the sublimation of the Te channel at elevated temperatures but also serves as the gate dielectric in top-gate devices operating at 1 V, achieving an on/off current ratio of 105.

Rahman, I K M Reaz↗
DOE OSTI2026

GaN Core-shell Nanofin Vertical Transistor (CoNVerT): A New Direction for Power Electronics (Final Scientific/Technical Report)

A novel power transistor architecture, the GaN c ore-shell n anofin ver tical transistor (CoNVerT) to address fundamental challenges in realizing the ultimate limit of GaN power transistor performance was explored experimentally. This technology promises ultra-high-efficiency high voltage/high power applications (e.g. DC/DC converters, motor control, fast charging, actuation), as well as to operate in harsh environments. The device exploits a vertical superjunction structure based on an experimentally-validated core-shell nanofin growth process in which lateral p-n heterojunctions are formed in a single growth step, while still maintaining vertical current flow for compact die size and low cost. The concept leverages the best properties of GaN for mid-range voltage applications: high mobility, high breakdown voltage, and native heterojunction enhancement-mode operation. Due to the crystallographic nature of the nanofin growth by molecular beam epitaxy, the sidewall heterojunctions occur on non-polar planes, resulting in ultra-smooth interfaces for high mobility, no sidewall etch damage and related surface/interface states, and elimination of piezoelectric effects that can limit reliability in conventional structures. This also facilitates superjunction formation for maximum device performance, and the selective-area growth of the nanofin results in dislocation-free growth, even on low-cost Si (111) substrate. In this program, core-shell nanofins were grown by molecular beam epitaxy, test structures to evaluate the doping, resistivity, and other electrical properties were fabricated, and the material and test structures were characterized in detail. The work identified clear potential (e.g., the doping was well controlled as required for superjunction concepts), but also additional areas that require additional effort to resolve (some unexpected crystal defects were encountered that require additional engineering to overcome). Simulation studies of the proposed concept validate that the fundamental approach is very promising, but additional effort in experimental realization is needed.

42 ENGINEERING↗
DOE OSTI2025

Organic Electrochemical Transistor Channel Materials: Copolymerization Versus Physical Mixing of Glycolated and Alkoxylated Polymers

Organic electrochemical transistors (OECTs) feature a polymer channel capable of conducting both ions and electronic charges. The choice of the channel material is critical for OECT performance. Many efforts have focused on improving performance via the chemical tunability of conjugated polymers – through backbone, side chain, and molar mass engineering – leading to useful design principles for accumulation-mode OECT materials. However, tuning the chemical structure of conjugated polymers often requires time-consuming optimization of the synthesis route. Meanwhile, variations in molar mass, dispersity, structural defects, and metal content present challenges when attempting to analyze the detailed effects of structural modifications, as multiple performance-determining factors are often (unintentionally) changed at the same time. Therefore, this study explores blended channel materials obtained by physically mixing glycolated and alkoxylated polymers in different ratios, and compares their OECT performance with the corresponding statistical copolymers. It is shown that mixing two well-performing materials creates blends that enable rational tuning of the transistor properties without compromising on performance. Thus, channels based on blends of alkoxylated and glycolated polymers hold promise for OECT technology with tailored response, as only two materials are needed to achieve any desired side chain ratio, simplifying the optimization of OECT characteristics.

copolymerization↗
DOE OSTI2025

Tunable 3D Aerosol Jet Printing of Low‐Power Redox‐Gated Transistors with Multicomponent Inks

Printed hybrid electronics (PHE) offer a promising alternative for microelectronics fabrication, addressing some limitations of traditional subtractive manufacturing. Despite the versatility of PHE, particularly in the customization of printing inks, these devices have not yet matched the performance of silicon-based electronics due to challenges in gating mechanisms and operational stability. However, the potential of low-voltage redox-gating to achieve significant carrier modulations in correlated metal oxides remains unexplored in PHE. This study systematically investigates vanadium dioxide (VO 2 ) nanoparticles and redox inks, linking their organization in solution to their morphology, phase state, and properties in solid films and multilayered structures. Using an aerosol jet printer (AJP), a solid-state VO 2 transistor is fabricated, operating at just 0.4 V gating voltage. The printed VO 2 films demonstrate redox-modulated conductivity and consistent transistor behavior. The solid-state redox gating materials also provide long-term stability, with the device maintaining performance over 6000 cycles without degradation. These results highlight the potential of redox gating to enhance the application of functional nanoparticles in printed hybrid microelectronics, especially for flexible, low-voltage, and energy-efficient devices.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Dendritic Computing with Multigate Ferroelectric Field-Effect Transistors

Although inspired by neuronal systems in the brain, artificial neural networks generally employ point-neurons, which offer computational complexity far less than that of their biological counterparts. Neurons have dendritic arbors that connect to different sets of synapses and offer local nonlinear accumulation – playing a pivotal role in processing and learning. Inspired by this, we propose a novel neuron design based on a multigate ferroelectric field-effect transistor that mimics dendrites. It leverages ferroelectric nonlinearity for local computations within dendritic branches while utilizing the transistor action to generate the neuronal output. The branched architecture enables smaller crossbar arrays in hardware integration, improving efficiency. Using an experimentally calibrated device-circuit-algorithm cosimulation framework, we demonstrate that networks incorporating our dendritic neurons achieve superior performance compared to much larger networks without dendrites (∼ 17× fewer trainable weight parameters). These findings suggest that dendritic hardware can significantly improve computational efficiency and learning capacity of neuromorphic systems optimized for edge applications.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Ambipolar Transport in Polycrystalline GeSn Transistors for Complementary Metal-Oxide-Semiconductor Applications

Group-IV alloy GeSn is a promising material for electronic and optoelectronic applications due to its compatibility with both Si substrates and established Si fabrication processes. This study focuses on polycrystalline GeSn (10% Sn), which offers a cost-effective, large-area, and versatile alternative to epitaxial GeSn. We demonstrate ambipolar transport behavior in polycrystalline GeSn thin film transistors, achieving electron and hole field-effect mobilities reaching up to 0.05 cm 2 /Vs and 2.05 cm 2 /Vs, respectively. Through temperature-dependent analysis, we elucidate the underlying mechanism of this phenomenon, which we attribute to quantum tunneling between the Schottky barrier contact and the channel, as well as potential barriers between the grain boundaries of this polycrystalline film, thereby advancing the understanding of polycrystalline GeSn's electrical properties. Furthermore, this work highlights the potential of ambipolar transport as a technique to employ towards the development of GeSn complementary metal-oxide-semiconductor field-effect transistors, promising to simplify and reduce the cost of GeSn manufacturing processes for edge computing and sensing applications.

42 ENGINEERING↗
DOE OSTI2026

Physical Modeling and Design of a Nonvolatile Optically Gated High‐Power Diamond Transistor

In this work, we present the theory and modeling framework of a diamond optically gated junction field‐effect transistor (DOGFET). The device utilizes nitrogen substitutional centers in type‐1b diamond to optically modulate a p‐ boron doped diamond channel. Using sub‐gap lasers with intensities as low as 100 W/cm 2 , electrons are optically excited from substitutional nitrogen sites to the conduction band of the diamond substrate, thus enabling the optical gate to exercise control on modulating the space‐charge region at the junction and therefore the channel conductivity. We show that the device can deliver a current of 7 μA/μm, or equivalently 1750 A/cm 2 , while switching at a frequency greater than 100 kHz, in a form factor of 5 μm 2 . The breakdown voltage is found to be greater than 1850 V, with a breakdown field strength of ~13 MV/cm. Moreover, the device supports nonvolatile operation with a “memory effect” enabling single transistor state retention. The presented simulation framework provides a physically grounded insight into the limits and opportunities of optoelectronic diamond systems.

Engineering - Electronic and electrical engineerin↗
DOE OSTI2025

Reversible parts-per-trillion-level detection of perfluorooctane sulfonic acid in tap water using field-effect transistor sensors

Widespread, persistent and toxic per- and polyfluoroalkyl substances (PFAS) pose a major threat to water systems and human health. Current detection methods are relatively expensive, slow and complex, underscoring the need for more accessible alternatives to meet increasingly stringent PFAS regulations. Here, in this study, we present an ultrasensitive sensing platform for perfluorooctane sulfonic acid detection in tap water with a reporting limit ( ~ 250 parts per quadrillion) lower than the US Environmental Protection Agency’s regulatory standard (4 parts per trillion), using a remote gate field-effect transistor featuring β-cyclodextrin (β-CD)-modified reduced graphene oxide as the sensing membrane. The sensor exhibits excellent selectivity against common inorganic ions, natural organic matter and select organic pollutants in tap water. The reversible and rapid response ( < 2 min) indicates the potential of remote gate field-effect transistor for continuous in-line monitoring. Mechanistic studies using quartz crystal microbalance and molecular dynamics simulations reveal key roles of analyte adsorption and charge properties in sensing performance and offer insights for designing more selective PFAS capture probes.

Wang, Yuqin [University of Chicago, IL (United Sta↗
DOE OSTI2025

Gate control of electron correlations towards Mott field effect transistors (MottFET)

The modulation of channel conductance in field-effect transistors (FETs) via metal-insulator-semiconductor structures has revolutionized information processing and storage. However, the limitations of silicon-based FETs in electrical switching have driven the search for new materials capable of overcoming these constraints. Electrostatic gating of competing electronic phases in a Mott material near its metal-to-insulator transition (MIT) offers the prospects of substantial modulation of the conducting electrons and electrical resistivity through small changes in band filling. While electrostatic control of the MIT has been previously reported, the advancement of Mott materials toward novel Mott-based transistors, MottFETs requires the realization of their unique physical properties in a solid-state device. In this study, we present gate control of electron correlation using a solid-state device utilizing the oxide Mott system La 1-x Sr x VO 3 as a correlated FET channel. We report on a gate resistance response that cannot be explained in a purely electrostatic framework. This behavior suggests an enhancement in effective mass and a reduction in effective carrier density as the system approaches its insulating state, consistent with theoretical predictions for Mott systems, suggesting at least 100× charge gain originating from the correlated behavior. These preliminary results pave the way toward the development of highly efficient, low-power electronic devices that could surpass the performance bottlenecks of conventional FETs by leveraging the electronic phase transitions of correlated electron systems.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗