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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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NASA-DoD Lead-Free Electronics Project
The primary technical objective of the project is to undertake comprehensive testing to generate information on failure modes/criteria to better understand the reliability of: Packages (e.g., TSOP, BGA, PDIP) assembled and reworked with lead-free alloys Packages (e.g., TSOP, BGA, PDIP) assembled and reworked with mixed (lead/lead-free) alloys.
NASA DOD Lead Free Electronics Project
The primary'technical objective of this project is to undertake comprehensive testing to generate information on failure modes/criteria to better understand the reliability of: Packages (e.g., Thin Small Outline Package [TSOP], Ball Grid Array [BGA], Plastic Dual In-line Package [PDIPD assembled and reworked with lead-free alloys Packages (e.g., TSOP, BGA, PDIP) assembled and reworked with mixed (lead/lead-free) alloys.
NASA-DoD Lead-Free Electronics Project
In response to concerns about risks from lead-free induced faults to high reliability products, NASA has initiated a multi-year project to provide manufacturers and users with data to clarify the risks of lead-free materials in their products. The project will also be of interest to component manufacturers supplying to high reliability markets. The project was launched in November 2006. The primary technical objective of the project is to undertake comprehensive testing to generate information on failure modes/criteria to better understand the reliability of: - Packages (e.g., TSOP, BGA, PDIP) assembled and reworked with solder interconnects consisting of lead-free alloys - Packages (e.g., TSOP, BGA, PDIP) assembled and reworked with solder interconnects consisting of mixed alloys, lead component finish/lead-free solder and lead-free component finish/SnPb solder.
NASA-DoD Lead-Free Electronics Project
In response to concerns about risks from lead-free induced faults to high reliability products, NASA has initiated a multi-year project to provide manufacturers and users with data to clarify the risks of lead-free materials in their products. The project will also be of interest to component manufacturers supplying to high reliability markets. The project was launched in November 2006. The primary technical objective of the project is to undertake comprehensive testing to generate information on failure modes/criteria to better understand the reliability of: (1) Packages (e.g., Thin Small Outline Package [TSOP], Ball Grid Array [BGA], Plastic Dual In-line Package [PDIP]) assembled and reworked with solder interconnects consisting of lead-free alloys (2) Packages (e.g., TSOP, BGA, PDIP) assembled and reworked with solder interconnects consisting of mixed alloys, lead component finish/lead-free solder and lead-free component finish/SnPb solder
NASA-DoD Lead-Free Electronics Project
The primary technical objective of this project is to undertake comprehensive testing to generate information on failure modes/criteria to better understand the reliability of: (1) Packages (e.g., Thin Small Outline Package [TSOP], Ball Grid Array [BGA], Plastic Dual In-line Package [PDIP]) assembled and reworked with lead-free alloys, (2) Packages (e.g., TSOP, BGA, PDIP) assembled and reworked with mixed (lead/lead-free) alloys.
NASA-DoD Lead-Free Electronics Project
In response to concerns about risks from lead-free induced faults to high reliability products, NASA has initiated a multi-year project to provide manufacturers and users with data to clarify the risks of lead-free materials in their products. The project will also be of interest to component manufacturers supplying to high reliability markets. The project was launched in November 2006. The primary technical objective of the project is to undertake comprehensive testing to generate information on failure modes/criteria to better understand the reliability of: - Packages (e.g., TSOP, BOA, PDIP) assembled and reworked with solder interconnects consisting of lead-free alloys - Packages (e.g., TSOP, BOA, PDIP) assembled and reworked with solder interconnects consisting of mixed alloys, lead component finish/lead-free solder and lead-free component finish/SnPb solder.
Thin Rechargeable Batteries for CMOS SRAM Memory Protection
New rechargeable battery technology is described and compared with classical primary battery back-up of SRAM PC cards. Thin solid polymer electrolyte cells with the thickness of TSOP memory components (1 mm nominal, 1.1 mm max) and capacities of 14 mAh/sq cm can replace coin cells. The SRAM PC cards with permanently installed rechargeable cells and optional electrochromic low battery voltage indicators will free the periodic PC card user from having to 'feed' their PC cards with coin cells and will allow a quick visual check of stored cards for their battery voltage status.
3D Chip Scale Package (CSP)
Package/die stacking technology enhances most aspects of electronic systems such as size, weight, speed, yield, and power consumption.
Vibration behavior of CSP assemblies with and without underfill
This paper presents vibration behavior of these assemblies along with optical and SEM cross-sectional micrographs taken after failures.