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Results for “Technology Aided Computer Design (TCAD)”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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12 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Simulation and Modeling of Time-Resolved X-Ray Detector for the Saturn Accelerator

In this work, we present the technology-aided computer design (TCAD) device simulation and modeling of a silicon p-i-n diode for detecting time-dependent X-ray radiation. We show that the simulated forward and reverse breakdown current–voltage characteristics agree well with the measured data under nonradiation environment by only calibrating carrier lifetimes for the forward bias case and avalanche model critical fields for the reverse bias condition. Using the calibrated parameters and other nominal material properties, we simulated the radiation responses of the p-i-n diode and compared with experimental data when the diode was exposed to X-ray radiation at Sandia’s Saturn facility and the Idaho State University (ISU) TriMeV facility. For Saturn’s Gaussian dose-rate pulses, we show three findings from TCAD simulations. First, the simulated photocurrents are in excellent agreement with the measured data for two dose-rate pulses with peak values of 1.16×10 10 and 1.88×10 10 rad(Si)/s. Second, the simulation results of high dose-rate pulses predict increased delayed photocurrents with longer time tails in the diode electrical responses due to excess carrier generation. Third, simulated peak values of diode radiation responses versus peak dose rates at different bias conditions provide useful guidance to determine the dose-rate range that the p-i-n diode can reliably detect in experiment. For TriMeV’s non-Gaussian dose-rate pulse, our simulated diode response is in decent agreement with the measured data without further calibration. We also studied the effects of device geometry, recombination process, and dose-rate enhancement via TCAD simulations to understand the higher measured response in the time after the peak dose-rate radiation for the p-i-n diode exposed to TriMeV irradiation.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2026

TCAD-Machine Learning Enabled TID Compact Model Development for Commercial SiC MOSFET

We propose a TCAD (Technology Computer Aided Design)-machine learning coupled approach that combines a TCAD tool (Charon), optimization/uncertainty quantification tool (Dakota), surrogate models, and Bayesian learning capabilities. The coupling approach is used for accurate modeling and calibration of total ionizing dose (TID) induced threshold voltage (V th ) shifts in Commercial-Off-The-Shelf (COTS) semiconductor devices and to develop physics-informed TID compact models. This versatile approach is applied to model the TID effect in an exemplar COTS 3.3 kV SiC power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). With the Charon-Dakota coupling, we can determine key device geometry and doping values based on device physics, which are difficult to obtain or not available for COTS devices but important for TCAD simulation; additionally, we can efficiently generate thousands of simulation results in a large parameter space, which makes it possible to develop data-driven surrogate models and perform Bayesian calibration. Utilizing the full tool-coupling approach, we achieve calibrated TCAD simulation models that accurately capture the average TID-induced V th shifts behavior with total doses and V th shifts saturation at high doses as observed in experimental data. More importantly, the calibrated TCAD simulations are obtained with determined TID model parameters (e.g., hole trap density and capture cross section) values that contain well quantified uncertainties. Furthermore, we can isolate and quantify the noises that are not captured by the TCAD models but exist in the measured data due to measurements and devices variabilities. Lastly, the calibrated surrogate models are used to develop physics-informed TID compact models. The method is generalizable to other devices and/or radiation conditions with few modifications and can provide well-determined uncertainties.

COTS↗
DOE OSTI2022

Physical Compact Model for Three-Terminal SONOS Synaptic Circuit Element

A well-posed physics-based compact model for a three-terminal silicon–oxide–nitride–oxide–silicon (SONOS) synaptic circuit element is presented for use by neuromorphic circuit/system engineers. Based on technology computer aided design (TCAD) simulations of a SONOS device, the model contains a nonvolatile memristor with the state variable QM representing the memristor charge under the gate of the three-terminal element. By incorporating the exponential dependence of the memristance on QM and the applied bias V for the gate, the compact model agrees quantitatively with the results from TCAD simulations as well as experimental measurements for the drain current. The compact model is implemented through VerilogA in the circuit simulation package Cadence Spectre and reproduces the experimental training behavior for the source–drain conductance of a SONOS device after applying writing pulses ranging from –12 V to +11 V, with an accuracy higher than 90%.

42 ENGINEERING↗
DOE OSTI2025

Prediction of Alpha-Particle-Immune Gate-All-Around Field-Effect Transistors (GAA-FET) Based SRAM Design

Alpha particles are known to be a major source of particles creating soft errors in semiconductor devices, such as content flipping in Static Random-Access Memory (SRAM). Recent advancements in transistor nodes have led to the introduction of Gate-All-Around Field Effect Transistors (GAA-FETs), which have better gate control, thus better electrostatics. Moreover, the introduction of bottom dielectric isolation (BDI) eliminates substrate leakage and thus is expected to enhance its radiation hardness. It is thus important to explore if one can design an SRAM that is completely radiation-hard to alpha particles. In this paper, using 3D Technology Computer-Aided-Design (TCAD) simulations, we show that it is possible to design an SRAM using GAA-FET technology so that it is immune to single alpha particle radiation error. In other words, with the design, there will be no single-event upset (SEU) due to alpha particles. We first use ab initio calculations in PHITS to show that there is a maximum linear energy transfer (LET), LET max , for the alpha particle in Si and Si x Ge 1-x . Based on that, by de signing a sub-7nm GAA-FET-based SRAM with BDI, we show that the SRAM does not flip even if the particle strike is in the worst-case scenario for LET > LET max .

42 ENGINEERING↗
DOE OSTI2024

CIGS Technology Advancement via Fundamental Modeling of Defect/Impurity Interactions (Final Technical Report)

The primary goals of the proposed work were to provide modeling tools (and the associated insight which comes along with model development) for design and optimization of CuIn x Ga 1-x Se 2 (CIGS) and CdSeTe (CST) solar cell manufacturing processes and to establish the foundation for comprehensive end-to-end predictive modeling tools to enable optimization of thin film photovoltaic technology for performance, cost, yield, and reliability. The initial focus of efforts within this project was to develop coupled process/optical/device models for CIGS PV technology and to work with Siva Power to apply that TCAD (technology computer-aided design) system to improve the efficiency and reduce manufacturing costs for CIGS solar cells. Our approach to that end was to generate an extensive database of DFT calculations and to use those calculations via statistical thermodynamics methods and Monte Carlo simulation to develop and characterize models for the behavior of native defects as well as intentional and unintentional impurities, including the redistribution of the primary components of CIGS films. Increased effort went toward coupling those models for defect behavior and composition evolution to the performance of multicrystalline CIGS solar cells via prediction of doping level and recombination lifetime as function of manufacturing process. In the second budget period, the project pivoted to developing a similar system for the CdSeTe system, focused especially on understanding the role of Se/Te alloy concentration. Execution of the project resulted in the successful development of TCAD systems for both CIGS and CdSeTe thin film PV within the Synopsys Sentaurus framework by utilizing the Alagator interface. In the first budget period of the project, we developed quantitative models for the major components of CIGS PV and implemented them within a framework that couples process, optical, and device simulation. From the insights we have gained, we identified novel opportunities for enhancing CIGS solar cell performance and have laid the groundwork to further optimize the layer structure, composition profile, and thermal cycles for substantially improved efficiency and lower manufacturing costs. For the CIGS system, process changes to achieve greater than 1% absolute enhancement in efficiency were identified, but testing of those approaches was stymied by lack of a domestic CIGS manufacturing partner after the closure of Siva Power as well as Miasole. For CdSeTe, a fully capable TCAD system only became ready to apply near the end of the project period, so substantial opportunities remain to apply those models to enhance the leading thin film PV technology.

14 SOLAR ENERGY↗
DOE OSTI2025

Dopant Optimization of Donors in Semiconductor Opening Switches to Eliminate Prepulse

Semiconductor opening switches are solid-state devices capable of delivering nanosecond, hundreds of kilovolts pulses by interrupting kiloamps of current. The interruption of the current occurs in a moderately doped p-region when a high electric field region (HFR) is formed. The HFR occurs because the reverse pumping current cannot be supported by the saturation velocity and majority carrier concentration of the doping level. However, the donor profile also significantly affects the pulse performance. A secondary prepulse occurs if a secondary HFR is formed at the interface of the background n-doping and N+ doping (X n ) . By moving the location of X n deeper into the diode, the effect of the prepulse is reduced. This article investigates the effect of the donor doping profile on the performance metrics of semiconductor opening switches through technology computer-aided design (TCAD) simulations and experimental results. Through a SILVACO TCAD optimization, we designed a P + /p/n - base/n/N + where the intersection of the moderate p-region and intrinsic n-base region (X p ) is at 160 μm and X n is at 220 μm. This profile is fabricated via silicon epitaxy. Experimentally, it is shown that a deep X n (220 μm) compared with a shallow X n (300 μm) reduces the rise time by >5× . In addition, the magnitude of current density during interruption affects the prepulse foot and pulse shape. At lower current densities without the graded donor profile, high peak voltages are not achieved. Comparing the experimental results to the TCAD simulations shows that the model is predictive under high-current densities in the semiconductor opening switch (SOS) regime.

nanosecond pulse power↗
DOE OSTI2023

Vertical van der Waals heterojunction diodes comprising 2D semiconductors on 3D β-Ga 2 O 3

Wide bandgap semiconductors such as gallium oxide (Ga 2 O 3 ) have attracted much attention for their use in next-generation high-power electronics. Although single-crystal Ga 2 O 3 substrates can be routinely grown from melt along various orientations, the influence of such orientations has been seldom reported. Further, making rectifying p–n diodes from Ga 2 O 3 has been difficult due to lack of p-type doping. In this study, we fabricated and optimized 2D/3D vertical diodes on β-Ga 2 O 3 by varying the following three factors: substrate planar orientation, choice of 2D material and metal contacts. Furthermore, the quality of our devices was validated using high-temperature dependent measurements, atomic-force microscopy (AFM) techniques and technology computer-aided design (TCAD) simulations. Our findings suggest that 2D/3D β-Ga 2 O 3 vertical heterojunctions are optimized by substrate planar orientation (–201), combined with 2D WS 2 exfoliated layers and Ti contacts, and show record rectification ratios (>10 6 ) concurrently with ON-Current density (>10 3 A cm –2 ) for application in power rectifiers.

36 MATERIALS SCIENCE↗
DOE OSTI2021

Low voltage drop tunnel junctions grown monolithically by MOCVD

Tunnel junction devices grown monolithically by metal organic chemical vapor deposition were optimized for minimization of the tunnel junction voltage drop. Here, two device structures were studied: an all-GaN homojunction tunnel junction and a graded InGaN heterojunction-based tunnel junction. This work reports a record-low voltage drop in the graded-InGaN heterojunction based tunnel junction device structure achieving a de-embedded tunnel junction voltage drop of 0.17 V at 100 A/cm 2 . The experimental data were compared with a theoretical model developed through technology computer-aided design (TCAD) simulations that offer a physics-based approach to understanding the key components of the design space, which lead to a more efficient tunnel junction.

42 ENGINEERING↗
DOE OSTI2022

A unified thermionic and thermionic-field emission (TE–TFE) model for ideal Schottky reverse-bias leakage current

We present a unified thermionic emission (TE) and thermionic-field emission (TFE) model for the ideal reverse-bias leakage current in Schottky junctions. The unified TE–TFE analytical model advances upon previous analytical TFE models by Murphy–Good and Padovani–Stratton, which are the two most widely adopted models by the community, in two major aspects: (i) the applicability of the TFE expression therein is extended to near-zero surface electric fields by an error-function correction, allowing for the calculation of the total current by a nontrivial sum of TE (over-the-barrier current) and TFE (below-the-barrier current) contributions; therefore, an accurate description of the TE-to-TFE transition region is captured analytically for the first time; (ii) image-force lowering is considered with much-simpler correction terms. Comparisons with the reference numerical model show that the unified TE–TFE model has excellent accuracy, as well as a 10 000× reduction in computation time. The unified model is further tested against experimental data from Schottky barrier diodes based on Si, 4H-SiC, GaN, and β-Ga 2 O 3 , revealing accurate extractions of barrier heights and correct descriptions of the ideal reverse leakage characteristics. With the extended applicable range, improved accuracy, and computational efficiency, the unified TE–TFE model is highly valuable for the design and analysis of devices based on Schottky junctions, as well as for potential integration in technology computer-aided design (TCAD) tools.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2024

Coupled Process/Device Modeling and Point Defect Engineering of Cu(In,Ga)Se 2 Solar Cells

Point defects directly impact solar cell device performance by limiting the carrier lifetime. In this work, density functional theory calculations are first used to determine the formation energy and diffusion energy barriers of dominant defects in Cu(In,Ga)Se 2 . Next, continuum reaction–diffusion models are developed to analyze the redistribution of defects during manufacturing processes. We estimate defect capture cross sections using a first-principles-based approach. Here, these cross sections are combined with our calculated defect profiles and trap energy levels to parameterize a Shockley–Read–Hall recombination model, which we implement into a device simulator to predict carrier lifetimes and device performance. In that way, a predictive technology computer aided design model is built to predict and optimize the performance of Cu(In,Ga)Se 2 solar cells.

14 SOLAR ENERGY↗
DOE OSTI2025

Understanding Reliability Trade-Offs in 1T-nC and 2T-nC FeRAM Designs

Ferroelectric random access memory (FeRAM) is a promising candidate for energy-efficient nonvolatile memory, particularly for logic-in-memory and compute-in-memory (CIM) applications. Among the available cell architectures, One-Transistor–n-Capacitor (1T-nC) and two-transistor–n-capacitor (2T-nC) FeRAMs each offer distinct trade-offs in density, scalability, and reliability. In this work, we present a comparative study of these two architectures under both dimensional scaling ( XY/Z shrinkage) and vertical integration (increasing stacked capacitors per cell). Using technology computer-aided design (TCAD) and circuit-level simulations, we analyze how scaling impacts ferroelectric capacitance, parasitic coupling, and floating-node (FN) dynamics, which together dictate sense margin (SM) and read stability. A key mitigation strategy—floating unselected capacitors—is applied to both architectures, effectively decoupling the SM from the number of stacked capacitors and enabling tractable analysis across scaling regimes. Results show that 1T-nC suffers more from charge sharing with the bitline (BL), while 2T-nC benefits from transistor isolation and stronger low-voltage sensing at the cost of increased area. By systematically evaluating these behaviors across scaling directions, this work establishes the reliability trade-offs of 1T-nC and 2T-nC cells and provides design guidelines for high-density, vertically integrated FeRAM systems.

1T-nC↗
DOE OSTI2025

Demonstration of Vertical 2T-nC FeRAM Hybrid Cell and Its Scalability for High-Density 3-D Ferroelectric Capacitor Memory

In this work, we present a comprehensive experimental and modeling study on the scaling of vertical 2T-nC ferroelectric random access memory (FeRAM) hybrid cells, comprising n metal-ferroelectric–metal (MFM) capacitors, to demonstrate a high-performance and high-density 3-D capacitor memory. Our contributions include: 1) successful process integration of vertical 2T-3C FeRAM cells by stacking MFM structures on top of Si CMOS transistors; 2) experimental validation of memory cell functionality, confirming the feasibility of the vertical 2T-nC FeRAM architecture; 3) an analysis of scaling effects on parasitic capacitance in densely integrated 3-D arrays, using 3-D technology computer-aided design (TCAD) simulations; 4) exploration of aggressive stacking of write bitlines (WBLs) to enhance memory density, where ferroelectric linear capacitance ( C FE ) enables self-boosted inhibition under the V W /2 scheme, but renders the V W /3 scheme ineffective due to intolerable write disturbances; and 5) assessment of horizontal scaling, revealing significant increases in read disturbances caused by interplane capacitance between adjacent WBLs ( C Z ). This work represents an early exploration into the potential of 2T-nC FeRAM as a scalable and efficient 3-D memory solution.

42 ENGINEERING↗