Temperature Effects on the Total Ionizing Dose Response of TaOx-based Memristive Bit Cells.
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This paper analyzes the total ionizing dose (TID) effects on noise characteristics of commercial multi-level-cell (MLC) 3-D NAND memory technology during the read operation. Additionally, the chips were exposed to a Co-60 gamma-ray source for up to 100 krad(Si) of TID. We find that the number of noisy cells in the irradiated chip increases with TID. Bit-flip noise was more dominant for cells in an erased state during irradiation compared to programmed cells.
Here, we demonstrate the utility of focused, pulsed X-rays for investigating localized total ionizing dose effects in bipolar analog integrated circuits. Using the LM139 comparator as a test vehicle, we show how the technique can be used to identify the sources of degradation as a result of irradiating different transistors of the device and how this impacts the input bias current, input offset voltage, and output voltage. The 2-D mapping of the sensitive regions of transistors is presented, where the results of localized irradiation impact the monitored operational parameters.
Here, total-ionizing-dose mechanisms are investigated in 16-nm InGaAs FinFETs with an HfO 2 /Al 2 O 3 gate-stack. Transistors are irradiated up to 500 krad(SiO 2 ) and annealed at high temperatures. Irradiated devices show negative threshold-voltage V th shifts, subthreshold stretch-out, and leakage current increases. These result from positive charge trapping in the gate oxide and shallow trench insulators, and increases in the interface and border-trap charge densities. Low-frequency noise measurements at different temperatures indicate a significant increase of noise magnitude in irradiated devices at an activation energy of ~0.4 eV. Density functional theory (DFT) calculations strongly suggest that transistor V th shifts are due primarily to hole trapping at oxygen vacancies in HfO 2 , and the increased noise is due primarily to O vacancies in Al 2 O 3 . Additional contributions to the noise from defects in the GaAs buffer layer are also likely, primarily at low temperatures.
This paper describes a new non-charge-based data storing technique in NAND flash memory called watermark that encodes read-only data in the form of physical properties of flash memory cells. Unlike traditional charge-based data storing method in flash memory, the proposed technique is resistant to total ionizing dose (TID) effects. To evaluate its resistance to irradiation effects, we analyze data stored in several commercial single-level-cell (SLC) flash memory chips from different vendors and technology nodes. These chips are irradiated using a Co-60 gamma-ray source array for up to 100 krad(Si) at Sandia National Laboratories. Experimental evaluation performed on a flash chip from Samsung shows that the intrinsic bit error rate (BER) of watermark increases from 0.8% for TID = 0 krad(Si) to 1% for TID = 100 krad(Si). Conversely, the BER of charge-based data stored on the same chip increases from 0% at TID = 0 krad(Si) to 1.5% at TID = 100 krad(Si). Overall, the results imply that the proposed technique may potentially offer significant improvements in data integrity relative to traditional charge-based data storage for very high radiation (TID > 100 krad(Si)) environments. These gains in data integrity relative to the charge-based data storage are useful in radiation-prone environments, but they come at the cost of increased write times and higher BERs before irradiation.
A multiscale modeling platform that supports the “virtual” qualification of commercial-off-the-shelf parts is presented. The multiscale approach is divided into two modules. The first module generates information related to the bipolar junction transistor gain degradation that is a function of fabrication process, operational, and environmental inputs. The second uses this information as inputs for radiation-enabled circuit simulations. The prototype platform described in this paper estimates the total ionizing dose and dose rate responses of linear bipolar integrated circuits for different families of components. The simulation and experimental results show good correlation and suggest this platform to be a complementary tool within the radiation-hardness assurance flow. Finally, the platform may reduce some of the costly reliance on testing for all systems.
This article evaluates the data retention characteristics of irradiated multi-level cell (MLC) 3-D NAND flash memories. We irradiate the memory chips by a Co-60 gamma-ray source for up to 50 krad(Si) and then write a random data pattern on the irradiated chip to find its retention characteristics. The experimental results show that the data retention property of the irradiated chips is significantly degraded compared to the un-irradiated ones. We evaluate two independent strategies to improve the data retention characteristics of the irradiated chips. Furthermore, the first method involves high-temperature annealing of the irradiated chip while the second method suggests pre-programming the memory modules before deploying them in radiation-prone environments.
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