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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2015

Materials Analysis and Modeling of Underfill Materials

The thermal-mechanical properties of three potential underfill candidate materials for PBGA applications are characterized and reported. Two of the materials are a formulations developed at Sandia for underfill applications while the third is a commercial product that utilizes a snap-cure chemistry to drastically reduce cure time. Viscoelastic models were calibrated and fit using the property data collected for one of the Sandia formulated materials. Along with the thermal-mechanical analyses performed, a series of simple bi-material strip tests were conducted to comparatively analyze the relative effects of cure and thermal shrinkage amongst the materials under consideration. Finally, current knowledge gaps as well as questions arising from the present study are identified and a path forward presented.

36 MATERIALS SCIENCE↗
NASA NTRS2013

Physics of Failure Analysis of Xilinx Flip Chip CCGA Packages: Effects of Mission Environments on Properties of LP2 Underfill and ATI Lid Adhesive Materials

The Xilinx Virtex 4QV and 5QV (V4 and V5) are next-generation field-programmable gate arrays (FPGAs) for space applications. However, there have been concerns within the space community regarding the non-hermeticity of V4/V5 packages; polymeric materials such as the underfill and lid adhesive will be directly exposed to the space environment. In this study, reliability concerns associated with the non-hermeticity of V4/V5 packages were investigated by studying properties and behavior of the underfill and the lid adhesvie materials used in V4/V5 packages.

Suh, Jong-ook↗
NASA NTRS2013

Physics of failure analysis of Xilinx Flip Chip CCGA packages: effects of mission environments on properties of LP2 underfill and ATI lid adhesive materials

The Xilinx Virtex 4QV and 5QV (V4 and V5) are next-generation field-programmable gate arrays (FPGAs) for space applications. However, there have been concerns within the space community regarding the non-hermeticity of V4/V5 packages; polymeric materials such as the underfill and lid adhesive will be directly exposed to the space environment. In this study, reliability concerns associated with the non-hermeticity of V4/V5 packages were investigated by studying properties and behavior of the underfill and the lid adhesvie materials used in V4/V5 packages.

Suh, Jong-ook↗
DOE OSTI2022

Experiments and modelling of adhesive failure initiation of an epoxy underfill: a study of electronic packaging survivability

Epoxy underfills can be implemented in electronic packaging to enhance solder joint reliability of surface mounted components. However, it is important for an engineer to have a failure criterion that can be used for failure predictions and redesign of electronic assemblies. For this study, data from epoxy bond failure in mock electronic part assemblies were correlated to finite element analyses to predict adhesive failure initiation. Experiments were performed to determine failure loads for various loading locations and nonlinear viscoelastic analyses were performed for the same loading locations to determine a maximum principal strain failure parameter. Predictions showed that a maximum principal strain failure parameter defined from one test could be used as an indicator of adhesive failure of an epoxy bond undergoing other modes of loading. Failure initiation predictions matched experimental data using a maximum principal strain failure parameter for an epoxy bond undergoing mixed modes of loading for both unfilled and alumina oxide filled 828DEA epoxy. Such experimental setup is deemed appropriate for future epoxy testing.

42 ENGINEERING↗
NASA NTRS2011

BOK-Underfill Optimization for FPGA Package/Assembly

Commercial-off-the-shelf area array package technologies in high-reliability versions are being considered for NASA electronic systems. These packages are prone to early failure due to the severe mechanical shock and vibration of launch, as well as other less severe conditions, such as mechanical loading during descent, rough terrain mobility, handling, and ground tests. As the density of these packages increases and the size of ball interconnections decrease, susceptibility to mechanical loading and cycling fatigue grows. This report presents a summary of the body of knowledge developed for the evaluation of area array packages and is based on surveys of literature from industry and academia. For high-reliability applications, the limited data that exists will be presented. Most data from industry deals with mechanical fatigue caused by four-point bend tests, as well as from drop tests for hand-held electronics; the most recent data will be presented, along with a brief background of prior literature. Understanding the key design guidelines and failure mechanisms from past tests is critical to developing an approach that will minimize future failures. Additional specific testing enables low-risk insertion of these advanced electronic packages.

mechanical fatigue↗
DOE OSTI2016

Thermal Testing Quality Assurance of 24LCC & 3LCC Electronic Packages

The purpose of this project is to experimentally validate the thermal fatigue life of solder interconnects for a variety of surface mount electronic packages. Over the years, there has been a significant amount of research and analysis in the fracture of solder joints on printed circuit boards. Solder is important in the mechanical and electronic functionality of the component. It is important throughout the life of the product that the solder remains crack and fracture free. The specific type of solder used in this experiment is a 63Sn37Pb eutectic alloy. Each package was manufactured with conformal coating along with and without an underfill material below the device. Conformal coating helps protect the board from environments such as electrostatic discharge and humidity. It is commonly used in broad types of engineering disciplines such as commercial, military, research and development, etc. Conformal coating can also pose a risk for the life of the board because of its high thermal expansion coefficient. This can greatly decrease the life of the product if it regularly sees high temperature variations. This leads to a shorter fatigue life of the solder. The fatigue life is a common mechanical problem in the field of electronic devices. Adding underfill can help increase the fatigue life of the solder. However, applying underfill adds time to manufacturing and production. This ultimately increases the cost per unit. The study of conformal coated printed circuit boards with and without underfill was done on two different surface mount electronic packages. The electronic packages studied were 24 and 3 contact Leadless Ceramic Chips packages. When the package was not underfilled, the coating was allowed to flow underneath. The assembly was analyzed and tested to obtain the best available combination of conformal coating, underfill, and potting to design the most robust and reliable circuit board while keeping in mind certain factors such as cost, manufacturing time, and need. Different types of conformal coatings were considered with and without underfill for each device. 29 of each component were manufactured to have a large sample size and for the sake of individual defects and imperfections. Finite Element Analysis (FEA) was performed by an engineer at Sandia National Laboratories for both Leadless Ceramic Chips. From the FEA results, a test acceleration profile was derived and the number of temperature cycles to fail the solder interconnects were found for three different cases. Experimentation was done as a secondary measure to validate this data to show confidence in the theoretical analysis. Accelerated testing functions as a quality check for the product. Accelerated testing is extremely useful in the research and development phase of engineering. It can save money from the potential of early life defects and the costs that come along with warranties. Accelerated testing makes a weaker design more robust and checks the reliability of a strong design in a shorter period of time. It is extremely helpful in a world where deliverables are in high demand and scheduling is tight. Accelerated testing helps the engineer gain an understanding of what needs to be improved and what works well. There are many different types of accelerated tests. Our circuit boards were accelerated inside a closed thermal chamber because of the high number of use cycles. The ultimate goal of this experimentation is to help identify what will prevent any premature cracking or fracturing in the solder alloy. It is important to understand that underfilling each component may or may not be needed. If underfill is not needed, there are several production benefits.

42 ENGINEERING↗
NASA NTRS2010

Advanced Flip Chips in Extreme Temperature Environments

The use of underfill materials is necessary with flip-chip interconnect technology to redistribute stresses due to mismatching coefficients of thermal expansion (CTEs) between dissimilar materials in the overall assembly. Underfills are formulated using organic polymers and possibly inorganic filler materials. There are a few ways to apply the underfills with flip-chip technology. Traditional capillary-flow underfill materials now possess high flow speed and reduced time to cure, but they still require additional processing steps beyond the typical surface-mount technology (SMT) assembly process. Studies were conducted using underfills in a temperature range of -190 to 85 C, which resulted in an increase of reliability by one to two orders of magnitude. Thermal shock of the flip-chip test articles was designed to induce failures at the interconnect sites (-40 to 100 C). The study on the reliability of flip chips using underfills in the extreme temperature region is of significant value for space applications. This technology is considered as an enabling technology for future space missions. Flip-chip interconnect technology is an advanced electrical interconnection approach where the silicon die or chip is electrically connected, face down, to the substrate by reflowing solder bumps on area-array metallized terminals on the die to matching footprints of solder-wettable pads on the chosen substrate. This advanced flip-chip interconnect technology will significantly improve the performance of high-speed systems, productivity enhancement over manual wire bonding, self-alignment during die joining, low lead inductances, and reduced need for attachment of precious metals. The use of commercially developed no-flow fluxing underfills provides a means of reducing the processing steps employed in the traditional capillary flow methods to enhance SMT compatibility. Reliability of flip chips may be significantly increased by matching/tailoring the CTEs of the substrate material and the silicon die or chip, and also the underfill materials. Advanced packaging interconnects technology such as flip-chip interconnect test boards have been subjected to various extreme temperature ranges that cover military specifications and extreme Mars and asteroid environments. The eventual goal of each process step and the entire process is to produce components with 100 percent interconnect and satisfy the reliability requirements. Underfill materials, in general, may possibly meet demanding end use requirements such as low warpage, low stress, fine pitch, high reliability, and high adhesion.

Ramesham, Rajeshuni↗
DOE OSTI2018

Delta size and plant patchiness as controls on channel network organization in experimental deltas

Understanding the feedbacks between water, sediment, and vegetation in deltas is an important part of understanding deltas as ecomorphodynamic systems. Here, we conducted a set of laboratory experiments using alfalfa (Medicago sativa) as a proxy for delta vegetation to investigate (1) the effects of plants on delta growth and channel network formation and (2) the timescales controlling delta evolution in the presence of plants. Experiments were conducted with fluctuating discharge (i.e. flood and base flow periods) and variable seeding densities. We found that when deltas were small, channels had no memory across flood cycles, as floods could completely fill the incised channel network. When deltas were large, the larger channel volume could remain underfilled to keep channel memory. Plant patches also helped to increase the number of channels and make a more distributive network. Patchiness increased over time to continually aid in bifurcation, but as vegetation cover and patch sizes increased, patches began to merge. Larger patches blocked the flow to enhance topset deposition and channel filling, even for the case of large deltas with a high channel volume. We conclude that both plant patchiness and delta size affect the development of the channel network, and we hypothesize that their influences are manifested through two competing timescales. The first timescale, T v , defines the time when the delta is large enough for channels to have memory (i.e., remain underfilled), and the second, T p , defines the time when vegetation patches merge, amplifying deposition and blocking channels. Finally, when run time is between these two timescales, the delta can develop a persistent distributary network of channels aided by bifurcation around plant patches, but once T p is reached, the channel network can again be destroyed by vegetation.

58 GEOSCIENCES↗
DOE OSTI2019

Numerical analysis of temperature and stress fields in hybrid indium antimonide arrays detector with laser irradiation

Thermal-stress effects are the major cause of failure in infrared focal-plane arrays detector, during laser irradiation. Based on the established three-dimensional structural model of hybrid indium antimonide infrared focal-plane arrays, the temperature and stress fields of hybrid indium antimonide detectors irradiated by 1.064-μm Gauss pulsed laser are studied, considering the temperature-dependent material parameters. The results indicate that the temperature increase and thermal stress effects are different, in each layer. Especially in indium antimonide chip, which is the uppermost layer of the indium antimonide detector that directly absorbs laser energy, the temperature shows not a smooth decrease as laser intensity from centre to outside, but a concentric-ringed ripple decrease with discontinuous high temperature extremum areas; which induces its own unique stress distributions: during the laser irradiation region, the thermal stress in areas above indium bumps is much lower than that in areas above underfill, but the stress distribution outside the laser irradiation region is exactly the opposite. The temperature and stress distribution in other materials are also different from that in indium antimonide chip. The main reason is that each material has different thermal properties, especially indium bump and underfill, which are alternative distribution in middle layers, have quite different thermal parameters. All these make the temperature and stress distribution in each layer having own characteristics. In addition, the change trend of the maximum temperature and stress in each layer in accordance with the laser pulse number are also studied. The maximum stress as well as temperature always occurs in the indium antimonide chip.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

Predictive dynamic wetting, fluid–structure interaction simulations for braze run-out

Brazing and soldering are metallurgical joining techniques that use a wetting molten metal to create a joint between two faying surfaces. Here, the quality of the brazing process depends strongly on the wetting properties of the molten filler metal, namely the surface tension and contact angle, and the resulting joint can be susceptible to various defects, such as run-out and underfill, if the material properties or joining conditions are not suitable. In this work, we implement a finite element simulation to predict the formation of such defects in braze processes. This model incorporates both fluid–structure interaction through an arbitrary Eulerian–Lagrangian technique and free surface wetting through conformal decomposition finite element modeling. Upon validating our numerical simulations against experimental run-out studies on a silver-Kovar system, we then use the model to predict run-out and underfill in systems with variable surface tension, contact angles, and applied pressure. Finally, we consider variable joint/surface geometries and show how different geometrical configurations can help to mitigate run-out. This work aims to understand how brazing defects arise and validate a coupled wetting and fluid–structure interaction simulation that can be used for other industrial problems.

36 MATERIALS SCIENCE↗