SEARCH · Search NASA

Results for “VLSI Neural Processor Design High Speed Image Data Compression SOI CMOS”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

SourceResearch connectionFrom yearThrough year

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

1 records

All sources NASA NTRS DOE OSTI

NASA NTRS1999

A Low-Power VLSI Neural Processor Design for High Speed Image Data Compression in a SOI CMOS Technology

This paper presents a low-power VLSI neural processor that has been developed for high-speed vision processing based upon the frequency-sensitive self-organization (FSO) neural algorithm.

VLSI Neural Processor Design High Speed Image Data↗