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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 19 records
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Cooling and Timing Tests of the ATLAS Fast TracKer VME Boards

The Fast TracKer (FTK) is an ATLAS trigger upgrade built for full-event, low-latency, high-rate tracking. The FTK core, made of 9U VME boards, performs the most demanding computational task. The associative memory board (AMB) serial link processor and the auxiliary card (AUX), plugged on the front and back sides of the same VME slot, constitute the processing unit (PU), which finds tracks using hits from eight layers of the inner detector. The PU works in pipeline with the second stage board (SSB), which finds 12-layer tracks by adding extra hits to the identified tracks. In the designed configuration, 16 PUs and four SSBs are installed in a VME crate. The high power consumption of the AMB, AUX, and SSB (respectively, of about 250, 70, and 160 W per board) required the development of a custom cooling system. Even though the expected power consumption for each VME crate of the FTK system is high compared with a common VME setup, the 8 FTK core crates will use ≈60 kW, which is just a fraction of the power and the space needed for a CPU farm performing the same task. We report on the integration of 32 PUs and eight SSBs inside the FTK system, on the infrastructures needed to run and cool them, and on the tests performed to verify the system processing rate and the temperature stability at a safe value.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
NASA NTRS2007

Soft Real-Time PID Control on a VME Computer

microPID (uPID) is a computer program for real-time proportional + integral + derivative (PID) control of a translation stage in a Fourier-transform ultraviolet spectrometer. microPID implements a PID control loop over a position profile at sampling rate of 8 kHz (sampling period 125microseconds). The software runs in a strippeddown Linux operating system on a VersaModule Eurocard (VME) computer operating in real-time priority queue using an embedded controller, a 16-bit digital-to-analog converter (D/A) board, and a laser-positioning board (LPB). microPID consists of three main parts: (1) VME device-driver routines, (2) software that administers a custom protocol for serial communication with a control computer, and (3) a loop section that obtains the current position from an LPB-driver routine, calculates the ideal position from the profile, and calculates a new voltage command by use of an embedded PID routine all within each sampling period. The voltage command is sent to the D/A board to control the stage. microPID uses special kernel headers to obtain microsecond timing resolution. Inasmuch as microPID implements a single-threaded process and all other processes are disabled, the Linux operating system acts as a soft real-time system.

Karayan, Vahag↗
NASA NTRS1992

VME rollback hardware for time warp multiprocessor systems

The purpose of the research effort is to develop and demonstrate innovative hardware to implement specific rollback and timing functions required for efficient queue management and precision timekeeping in multiprocessor discrete event simulations. The previously completed phase 1 effort demonstrated the technical feasibility of building hardware modules which eliminate the state saving overhead of the Time Warp paradigm used in distributed simulations on multiprocessor systems. The current phase 2 effort will build multiple pre-production rollback hardware modules integrated with a network of Sun workstations, and the integrated system will be tested by executing a Time Warp simulation. The rollback hardware will be designed to interface with the greatest number of multiprocessor systems possible. The authors believe that the rollback hardware will provide for significant speedup of large scale discrete event simulation problems and allow multiprocessors using Time Warp to dramatically increase performance.

Robb, Michael J.↗
DOE OSTI2020

WIRE SCANNER FOR HIGH INTENSITY BEAM PROFILE DIAGNOSITICS

A control and data acquisition system of a high speed wire scanner is developed for high intensity beam profile diagnostics. The control system of the wire scanner includes two IOCs, a Soft IOC and a VME IOC. The Soft IOC connects with an Aerotech Ensemble motor drive through EPCIS motor record and controls the movement of the wire scanner. An Electrical Input card samples the real-time position of the wire through an incremental encoder, and generates a pulse to synchronize a VME ADC data acquisition card, which digitizes and samples the beam-induced signal after pre-amplification. A VME Relay Output card is installed to control the Brake Solenoid and Actuator Solenoid. All the VME I/O cards are installed on one VME crate and controlled by the VME IOC. The system configuration and software of the wire scanner are under development.

Yan, J.↗
NASA NTRS1997

Development of a Production Ready Automated Wire Delivery System

The current development effort is a Phase 3 research study entitled "A Production Ready Automated Wire Delivery System", contract number NAS8-39933, awarded to Nichols Research Corporation (NRC). The goals of this research study were to production harden the existing Automated Wire Delivery (AWDS) motion and sensor hardware and test the modified AWDS in a range of welding applications. In addition, the prototype AWDS controller would be moved to the VME bus platform by designing, fabricating and testing a single board VME bus AWDS controller. This effort was to provide an AWDS that could transition from the laboratory environment to production operations. The project was performed in two development steps. Step 1 modified and tested an improved MWG. Step 2 developed and tested the AWDS single board VME bus controller. Step 3 installed the Wire Pilot in a Weld Controller with the imbedded VME bus controller.

Source record↗
NASA NTRS1990

Custom electronic subsystems for the laboratory telerobotic manipulator

The National Aeronautics and Space Administration (NASA) Space Station Program presents new opportunities for the application of telerobotic and robotic systems. The Laboratory Telerobotic Manipulator (LTM) is a highly advanced 7 degrees-of-freedom (DOF) telerobotic/robotic manipulator. It was developed and built for the Automation Technology Branch at NASA's Langley Research Center (LaRC) for work in research and to demonstrate ground-based telerobotic manipulator system hardware and software systems for future NASA applications in the hazardous environment of space. The LTM manipulator uses an embedded wiring design with all electronics, motor power, and control and communication cables passing through the pitch-yaw differential joints. This design requires the number of cables passing through the pitch/yaw joint to be kept to a minimum. To eliminate the cables needed to carry each pitch-yaw joint's sensor data to the VME control computers, a custom-embedded electronics package for each manipulator joint was developed. The electronics package collects and sends the joint's sensor data to the VME control computers over a fiber optic cable. The electronics package consist of five individual subsystems: the VME Link Processor, the Joint Processor and the Joint Processor power supply in the joint module, the fiber optics communications system, and the electronics and motor power cabling.

Glassell, R. L.↗
NASA NTRS2001

Lessons Learned Using COTS Electronics for the International Space Station Radiation Environment

The mantra of 'Faster, Better, Cheaper' has to a large degree been interpreted as using Commercial Off-the-Shelf (COTS) components and/or circuit boards. One of the first space applications to actually use COTS in space along with radiation performance requirements was the Expedite the Processing of Experiments to Space Station (EXPRESS) Rack program, for the International Space Station (ISS). In order to meet the performance, cost and schedule targets, military grade Versa Module Eurocard (VME) was selected as the baseline design for the main computer, the Rack Interface Controller (RIC). VME was chosen as the computer backplane because of the large variety of military grade boards available, which were designed to meet the military environmental specifications (thermal, shock, vibration, etc.). These boards also have a paper pedigree in regards to components. Since these boards exceeded most ISS environmental requirements, it was reasoned using COTS mid-grade VME boards, as opposed to designing custom boards could save significant time and money. It was recognized up front the radiation environment of ISS, while benign compared to many space flight applications, would be the main challenge to using COTS. Thus in addition to selecting vendors on how well their boards met the usual performance and environmental specifications, the board's parts lists were reviewed on how well they would perform in the ISS radiation environment. However, issues with verifying that the available radiation test data was applicable to the actual part used, vendor part design changes and the fact most parts did not have valid test data soon complicated board and part selection in regards to radiation.

Blumer, John H.↗
NASA NTRS2003

Signal-Conditioning Amplifier Recorders

Signal-conditioning amplifier recorders (SCAmpRs) have been proposed as a means of simplifying and upgrading the Kennedy Space Center (KSC) Ground Measurement System (GMS), which is a versatile data-acquisition system that gathers and records a variety of measurement data before and during the launch of a space shuttle. In the present version of the GMS system, signal conditioning amplifiers digitize and transmit data to a VME chassis that multiplexes up to 416 channels. The data is transmitted via a high-speed data bus to a second VME chassis where it is available for snapshots. The data is passed from the second VME chassis to a high-speed data recorder. This process is duplicated for installations at two launch pads and the Vehicle Assembly Building (VAB). Since any failure of equipment in the data path results in loss of data, much of the system is redundant. The architecture of the existing GMS limits expansion or any modification to the system to meet changing requirements because of the cost and time required. A SCAmpR-based system is much more flexible. The basis of the simplification, flexibility, and reliability is the shifting of the recording function to the individual amplifier channels. Each SCAmpR is a self-contained single channel data acquisition system, which in its current implementation, has a data storage capacity of up to 30 minutes when operating at the fastest data sampling rates. The SCAmpR channels are self-configuring and self-calibrating. Multiple SCAmpR channels are ganged on printed circuit boards and mounted in a chassis that provides power, a network hub, and Inter-Range Instrument Group (IRIG) time signals. The SCAmpR channels share nothing except physical mounting on a circuit board. All circuitry is electrically separate for each channel. All that is necessary to complete the data acquisition system is a single master computer tied to the SCAmpR channels by standard network equipment. The size of the data acquisition system dictates the requirements for the specific network equipment.

Medelius, Pedro J.↗
NASA NTRS2003

A Timer for Synchronous Digital Systems

The Real-Time Interferometer Control Systems Testbed (RICST) timing board is a VersaModule Eurocard (VME)-based board that can generate up to 16 simultaneous, phase-locked timing signals at a rate defined by the user. It can also generate all seven VME interrupt requests (IRQs). The RICST timing board is suitable mainly for robotic, aerospace, and real-time applications. Several circuit boards on the market are capable of generating periodic IRQs. Most are associated with Global Positioning System (GPS) receivers and Inter Range Instrumentation Group (IRIG) time-code generators, whereas this board uses either an internal VME clock or an externally generated clock signal to synchronize multiple components of the system. The primary advantage of this board is that there is no discernible jitter in the output clock waveforms because the signals are divided down from a high-frequency clock signal instead of being phase-locked from a lower frequency. The primary disadvantage to this board, relative to other periodic-IRQ-generating boards, is that it is more difficult to synchronize the system to wall clock time.

McKenney, Elizabeth↗
DOE OSTI2022

A Modern Ethernet Data Acquisition Architecture for Fermilab Beam Instrumentation

The Fermilab Accelerator Division, Instrumentation Department is adopting an open-source framework to replace our embedded VME-based data acquisition systems. Utilizing an iterative methodology, we first moved to embedded Linux, removing the need for VxWorks. Next, we adopted Ethernet on each data acquisition module eliminating the need for the VME backplane in addition to communicating with a rack mount server. Development of DDCP (Distributed Data Communications Protocol), allowed for an abstraction between the firmware and software layers. Each data acquisition module was adapted to read out using 1 GbE and aggregated at a switch which up linked to a 10 GbE network. Current development includes scaling the system to aggregate more modules, to increase bandwidth to support multiple systems and to adopt MicroTCA as a crate technology. The architecture was utilized on various beamlines around the Fermilab complex including PIP2IT, FAST/IOTA and the Muon Delivery Ring. In summary, we were able to develop a data acquisition framework which incrementally replaces VxWorks & VME hardware as well as increases our total bandwidth to 10 Gbit/s using off the shelf Ethernet technology.

43 PARTICLE ACCELERATORS↗
DOE OSTI2024

FY2024 Q4 L2 Milestone 8237 for Opacity-on-NIF

This document addresses parts 2 and 3 of the original milestone request. In the following writeup, the development of OpSpecTR at LLNL by LLNL and NNSS personnel will be detailed first, followed by a write-up of the development of Vme-resolved simulaVons of the opacity-on-NIF experiment. Capsule backlight simulaVons, hohlraum simulaVons, and sample simulaVons from CASSIO are combined to produce the line of sight from the capsule to an effecVve OpSpec posiVon. Spectra are generated by post-processing these simulaVons from either Spect3D, a commercial software by Prism ComputaVonal Sciences, or FESTR (Finite Element Spectroscopic Transport of RadiaVon), a LANL code. While the simulaVons do not at this stage proceed late enough to include the worst of the backgrounds generated from the hohlraum experimentally and each post-processing simulaVon includes only one ray for each spectrometer channel, these efforts represent proof of concept for a new capability to complete Vme-resolved and Vmegated simulaVons for the complete line of sight of the complex opacity-on-NIF geometry. Future work will be discussed at the end of the report for both efforts.

42 ENGINEERING↗
NASA NTRS1989

Conference on Real-Time Computer Applications in Nuclear, Particle and Plasma Physics, 6th, Williamsburg, VA, May 15-19, 1989, Proceedings

Papers on real-time computer applications in nuclear, particle, and plasma physics are presented, covering topics such as expert systems tactics in testing FASTBUS segment interconnect modules, trigger control in a high energy physcis experiment, the FASTBUS read-out system for the Aleph time projection chamber, a multiprocessor data acquisition systems, DAQ software architecture for Aleph, a VME multiprocessor system for plasma control at the JT-60 upgrade, and a multiasking, multisinked, multiprocessor data acquisition front end. Other topics include real-time data reduction using a microVAX processor, a transputer based coprocessor for VEDAS, simulation of a macropipelined multi-CPU event processor for use in FASTBUS, a distributed VME control system for the LISA superconducting Linac, a distributed system for laboratory process automation, and a distributed system for laboratory process automation. Additional topics include a structure macro assembler for the event handler, a data acquisition and control system for Thomson scattering on ATF, remote procedure execution software for distributed systems, and a PC-based graphic display real-time particle beam uniformity.

Pordes, Ruth↗
NASA NTRS2001

Flight Computer Processing Avionics for Space Station Microgravity Experiments: A Risk Assessment of Commercial Off-the-Shelf Utilization

NASA/Marshall Space Flight Center (MSFC) is continually looking for ways to reduce the costs and schedule and minimize the technical risks during the development of microgravity programs. One of the more prominent ways to minimize the cost and schedule is to use off-the-shelf hardware (OTS). However, the use of OTS often increases the risk. This paper addresses relevant factors considered during the selection and utilization of commercial off-the-shelf (COTS) flight computer processing equipment for the control of space station microgravity experiments. The paper will also discuss how to minimize the technical risks when using COTS processing hardware. Two microgravity experiments for which the COTS processing equipment is being evaluated for are the Equiaxed Dendritic Solidification Experiment (EDSE) and the Self-diffusion in Liquid Elements (SDLE) experiment. Since MSFC is the lead center for Microgravity research, EDSE and SDLE processor selection will be closely watched by other experiments that are being designed to meet payload carrier requirements. This includes the payload carriers planned for the International Space Station (ISS). The purpose of EDSE is to continue to investigate microstructural evolution of, and thermal interactions between multiple dendrites growing under diffusion controlled conditions. The purpose of SDLE is to determine accurate self-diffusivity data as a function of temperature for liquid elements selected as representative of class-like structures. In 1999 MSFC initiated a Center Director's Discretionary Fund (CDDF) effort to investigate and determine the optimal commercial data bus architecture that could lead to faster, better, and lower cost data acquisition systems for the control of microgravity experiments. As part of this effort various commercial data acquisition systems were acquired and evaluated. This included equipment with various form factors, (3U, 6U, others) and equipment that utilized various bus structures, (VME, PC104, STD bus). This evaluation of hardware was performed in conjunction with a trade study that considered over twenty (20) different factors relevant to the selection of an optimum design approach. These factors included; safety, sizing and timing, radiation hardness and single event upset, power consumption, heat dissipation, size and volume, expected service life, maintainability, heritage, operating systems, requirements for software reuse, availability of compatible interface boards, relative cost, schedule, reliability, EMI/EMC factors, "hot swap" capability, standards for conduction cooling, I/O capabilities, unique carrier requirements and operating system considerations. The approach to evaluate Safety as part of this study included a review of the Preliminary Hazard Analysis (PHA) for each of the experiment designs and a determination of how each hazard could be addressed and eliminated when different processors were selected. This included evaluating various design approaches and trade-offs between fault tolerant designs and fail-safe designs in accordance with NSTS 1700.7B. This will include the results of radiation testing where available. Various operating systems, such as VxWorks, Linux, QNX, and Embedded NT are evaluated and the advantages and disadvantages of their utilization are also addressed. Design implementation strategies for the various operating systems are considered and discussed. This paper presents the results and recommendations from this trade study. Preliminary conclusions from this study are that safety concerns from lack or radiation testing on COTS equipment can be addressed by additional testing and design considerations, the PC104 bus provided adequate I/O for the SDLE and EDSE microgravity experiments, and PC104 bus components offered significant advantages over VME and cPCI for weight and space reductions.

Estes, Howard↗
NASA NTRS2001

Determination of an Optimal Commercial Data Bus Architecture for a Flight Data System

NASA/Marshall Space Flight Center (MSFC) is continually looking for methods to reduce cost and schedule while keeping the quality of work high. MSFC is NASA's lead center for space transportation and microgravity research. When supporting NASA's programs several decisions concerning the avionics system must be made. Usually many trade studies must be conducted to determine the best ways to meet the customer's requirements. When deciding the flight data system, one of the first trade studies normally conducted is the determination of the data bus architecture. The schedule, cost, reliability, and environments are some of the factors that are reviewed in the determination of the data bus architecture. Based on the studies, the data bus architecture could result in a proprietary data bus or a commercial data bus. The cost factor usually removes the proprietary data bus from consideration. The commercial data bus's range from Versa Module Eurocard (VME) to Compact PCI to STD 32 to PC 104. If cost, schedule and size are prime factors, VME is usually not considered. If the prime factors are cost, schedule, and size then Compact PCI, STD 32 and PC104 are the choices for the data bus architecture. MSFC's center director has funded a study from his discretionary fund to determine an optimal low cost commercial data bus architecture. The goal of the study is to functionally and environmentally test Compact PCI, STD 32 and PC 104 data bus architectures. This paper will summarize the results of the data bus architecture study.

Crawford, Kevin↗
DOE OSTI2022

Synchronous High-frequency Distributed Readout For Edge Processing At The Fermilab Main Injector And Recycler

The Main Injector (MI) was commissioned using data acquisition systems developed for the Fermilab Main Ring in the 1980s. New VME-based instrumentation was commissioned in 2006 for beam loss monitors (BLM)[2], which provided a more systematic study of the machine and improved displays of routine operation. However, current projects are demanding more data and at a faster rate from this aging hardware. One such project, Real-time Edge AI for Distributed Systems (READS), requires the high-frequency, low-latency collection of synchronized BLM readings from around the approximately two-mile accelerator complex. Significant work has been done to develop new hardware to monitor the VME backplane and broadcast BLM measurements over Ethernet, while not disrupting the existing operations critical functions of the BLM system. This paper will detail the design, implementation, and testing of this parallel data pathway.

43 PARTICLE ACCELERATORS↗
DOE OSTI2024

New Insertion Device Control System for the APS Upgrade

New Hybrid Permanent Magnet Undulators (HPMUs) have been designed and manufactured using servo motors for precise and reliable gap motion control for the Advanced Photon Source Upgrade (APS-U) project. Meanwhile, existing HPMUs equipped with legacy stepper motors are systematically replaced with servo motors. In parallel with mechanical modifications of the undulators, a comprehensive upgrade has been implemented for the control of the devices. This upgrade includes integration of standardized industrial components for replacement of motor controllers and motor drives using the Kollmorgen Programmable Controller Multi-axis Master (PCMM) controllers and the AKD2G series servo drives. Soft Input Output Controllers (IOCs) are developed and deployed to replace the legacy VME-based IOCs for both single-period undulators and Revolver undulators. In this paper, we will present the architecture of the new insertion device control system, including control mechanisms, interlock protocols, and tools for diagnostics and troubleshooting.

Li, W.↗
DOE OSTI2020

A VXS [VITA41] Trigger Processor for the 12GEV Experimental Programs at Jefferson Lab

The VXS_Trigger_Processor [VTP] was developed and commissioned for CLAS12 in the fall of 2016. This board is a VITA41 switch card and it collects data from a variety of front-end TDC and Flash ADC modules. The VTP has since been used in several experiments at Jefferson Lab serving as the L1 trigger module for a variety of detector types, such as stacked calorimeters, strip calorimeters, time-of-flight, Cerenkov, hodoscopes, drift chambers, and silicon strips. Trigger algorithms implemented include cluster finding (1D, 2D), drift chamber segment and road finding, geometry matching between various detectors, particle counting, and general global trigger bit processing. The VTP is also capable of reading out each front-end crate with up to 40Gbps Ethernet which is an enormous increase compared to the currently used 200MB/s VME bus. Recent progress has been made to show that a firmware and software upgrade can enable existing Jefferson Lab front-end crates to operate in a streaming DAQ mode. In February 2020, tests will be performed on a full calorimeter and matched hodoscope which are components of the CLAS12 Forward Tagger detector system with beam in Hall B. This paper details the hardware performance, triggered, and streaming applications that have been implemented using the VTP for several experiments at Jefferson Lab.

ABBOTT, David↗
DOE OSTI2022

Multi-Frame Gated X-Ray Imager Report

The Multi-Frame Gated X-ray Imager (MGXI) project for the Lawrence Livermore National Laboratory (LLNL) with Project Leader Arthur Carpenter has finished its third year of collaboration with PI Charles Hunt in the ECE Department at UC Davis. This Target Area Science Engineering (TASE) project is part of the National Ignition Facility (NIF) and receives federal funding from the Department of Energy under contract B639825 for the Vacuum Microelectronics (VME) Group to conduct the yearly objectives. The ultimate goal is to construct a burst-mode x-ray imager with multiple frames with as low as ≤25μm spatial resolution and 50ps temporal resolution for use with x-rays in the 5-75keV range; and when coupled to an optically sensitive transmission photocathode (such as an S20) 400-700nm visible range.

42 ENGINEERING↗