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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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Cooling and Timing Tests of the ATLAS Fast TracKer VME Boards

The Fast TracKer (FTK) is an ATLAS trigger upgrade built for full-event, low-latency, high-rate tracking. The FTK core, made of 9U VME boards, performs the most demanding computational task. The associative memory board (AMB) serial link processor and the auxiliary card (AUX), plugged on the front and back sides of the same VME slot, constitute the processing unit (PU), which finds tracks using hits from eight layers of the inner detector. The PU works in pipeline with the second stage board (SSB), which finds 12-layer tracks by adding extra hits to the identified tracks. In the designed configuration, 16 PUs and four SSBs are installed in a VME crate. The high power consumption of the AMB, AUX, and SSB (respectively, of about 250, 70, and 160 W per board) required the development of a custom cooling system. Even though the expected power consumption for each VME crate of the FTK system is high compared with a common VME setup, the 8 FTK core crates will use ≈60 kW, which is just a fraction of the power and the space needed for a CPU farm performing the same task. We report on the integration of 32 PUs and eight SSBs inside the FTK system, on the infrastructures needed to run and cool them, and on the tests performed to verify the system processing rate and the temperature stability at a safe value.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

WIRE SCANNER FOR HIGH INTENSITY BEAM PROFILE DIAGNOSITICS

A control and data acquisition system of a high speed wire scanner is developed for high intensity beam profile diagnostics. The control system of the wire scanner includes two IOCs, a Soft IOC and a VME IOC. The Soft IOC connects with an Aerotech Ensemble motor drive through EPCIS motor record and controls the movement of the wire scanner. An Electrical Input card samples the real-time position of the wire through an incremental encoder, and generates a pulse to synchronize a VME ADC data acquisition card, which digitizes and samples the beam-induced signal after pre-amplification. A VME Relay Output card is installed to control the Brake Solenoid and Actuator Solenoid. All the VME I/O cards are installed on one VME crate and controlled by the VME IOC. The system configuration and software of the wire scanner are under development.

Yan, J.↗

A Modern Ethernet Data Acquisition Architecture for Fermilab Beam Instrumentation

The Fermilab Accelerator Division, Instrumentation Department is adopting an open-source framework to replace our embedded VME-based data acquisition systems. Utilizing an iterative methodology, we first moved to embedded Linux, removing the need for VxWorks. Next, we adopted Ethernet on each data acquisition module eliminating the need for the VME backplane in addition to communicating with a rack mount server. Development of DDCP (Distributed Data Communications Protocol), allowed for an abstraction between the firmware and software layers. Each data acquisition module was adapted to read out using 1 GbE and aggregated at a switch which up linked to a 10 GbE network. Current development includes scaling the system to aggregate more modules, to increase bandwidth to support multiple systems and to adopt MicroTCA as a crate technology. The architecture was utilized on various beamlines around the Fermilab complex including PIP2IT, FAST/IOTA and the Muon Delivery Ring. In summary, we were able to develop a data acquisition framework which incrementally replaces VxWorks & VME hardware as well as increases our total bandwidth to 10 Gbit/s using off the shelf Ethernet technology.

43 PARTICLE ACCELERATORS↗

FY2024 Q4 L2 Milestone 8237 for Opacity-on-NIF

This document addresses parts 2 and 3 of the original milestone request. In the following writeup, the development of OpSpecTR at LLNL by LLNL and NNSS personnel will be detailed first, followed by a write-up of the development of Vme-resolved simulaVons of the opacity-on-NIF experiment. Capsule backlight simulaVons, hohlraum simulaVons, and sample simulaVons from CASSIO are combined to produce the line of sight from the capsule to an effecVve OpSpec posiVon. Spectra are generated by post-processing these simulaVons from either Spect3D, a commercial software by Prism ComputaVonal Sciences, or FESTR (Finite Element Spectroscopic Transport of RadiaVon), a LANL code. While the simulaVons do not at this stage proceed late enough to include the worst of the backgrounds generated from the hohlraum experimentally and each post-processing simulaVon includes only one ray for each spectrometer channel, these efforts represent proof of concept for a new capability to complete Vme-resolved and Vmegated simulaVons for the complete line of sight of the complex opacity-on-NIF geometry. Future work will be discussed at the end of the report for both efforts.

42 ENGINEERING↗

Synchronous High-frequency Distributed Readout For Edge Processing At The Fermilab Main Injector And Recycler

The Main Injector (MI) was commissioned using data acquisition systems developed for the Fermilab Main Ring in the 1980s. New VME-based instrumentation was commissioned in 2006 for beam loss monitors (BLM)[2], which provided a more systematic study of the machine and improved displays of routine operation. However, current projects are demanding more data and at a faster rate from this aging hardware. One such project, Real-time Edge AI for Distributed Systems (READS), requires the high-frequency, low-latency collection of synchronized BLM readings from around the approximately two-mile accelerator complex. Significant work has been done to develop new hardware to monitor the VME backplane and broadcast BLM measurements over Ethernet, while not disrupting the existing operations critical functions of the BLM system. This paper will detail the design, implementation, and testing of this parallel data pathway.

43 PARTICLE ACCELERATORS↗

New Insertion Device Control System for the APS Upgrade

New Hybrid Permanent Magnet Undulators (HPMUs) have been designed and manufactured using servo motors for precise and reliable gap motion control for the Advanced Photon Source Upgrade (APS-U) project. Meanwhile, existing HPMUs equipped with legacy stepper motors are systematically replaced with servo motors. In parallel with mechanical modifications of the undulators, a comprehensive upgrade has been implemented for the control of the devices. This upgrade includes integration of standardized industrial components for replacement of motor controllers and motor drives using the Kollmorgen Programmable Controller Multi-axis Master (PCMM) controllers and the AKD2G series servo drives. Soft Input Output Controllers (IOCs) are developed and deployed to replace the legacy VME-based IOCs for both single-period undulators and Revolver undulators. In this paper, we will present the architecture of the new insertion device control system, including control mechanisms, interlock protocols, and tools for diagnostics and troubleshooting.

Li, W.↗

A VXS [VITA41] Trigger Processor for the 12GEV Experimental Programs at Jefferson Lab

The VXS_Trigger_Processor [VTP] was developed and commissioned for CLAS12 in the fall of 2016. This board is a VITA41 switch card and it collects data from a variety of front-end TDC and Flash ADC modules. The VTP has since been used in several experiments at Jefferson Lab serving as the L1 trigger module for a variety of detector types, such as stacked calorimeters, strip calorimeters, time-of-flight, Cerenkov, hodoscopes, drift chambers, and silicon strips. Trigger algorithms implemented include cluster finding (1D, 2D), drift chamber segment and road finding, geometry matching between various detectors, particle counting, and general global trigger bit processing. The VTP is also capable of reading out each front-end crate with up to 40Gbps Ethernet which is an enormous increase compared to the currently used 200MB/s VME bus. Recent progress has been made to show that a firmware and software upgrade can enable existing Jefferson Lab front-end crates to operate in a streaming DAQ mode. In February 2020, tests will be performed on a full calorimeter and matched hodoscope which are components of the CLAS12 Forward Tagger detector system with beam in Hall B. This paper details the hardware performance, triggered, and streaming applications that have been implemented using the VTP for several experiments at Jefferson Lab.

ABBOTT, David↗

Multi-Frame Gated X-Ray Imager Report

The Multi-Frame Gated X-ray Imager (MGXI) project for the Lawrence Livermore National Laboratory (LLNL) with Project Leader Arthur Carpenter has finished its third year of collaboration with PI Charles Hunt in the ECE Department at UC Davis. This Target Area Science Engineering (TASE) project is part of the National Ignition Facility (NIF) and receives federal funding from the Department of Energy under contract B639825 for the Vacuum Microelectronics (VME) Group to conduct the yearly objectives. The ultimate goal is to construct a burst-mode x-ray imager with multiple frames with as low as ≤25μm spatial resolution and 50ps temporal resolution for use with x-rays in the 5-75keV range; and when coupled to an optically sensitive transmission photocathode (such as an S20) 400-700nm visible range.

42 ENGINEERING↗

Redis-Based Streaming Architecture for Accelerator Beam Instrumentation DAQ Systems

The Fermilab Acceleraor Division, Beam Instrumentation Department, is always adopting modern and current software methodologies for complex DAQ architectures. This paper highlights the Redis Adapter (RA) as the key software component enabling high performance, modular communication between digitizers and distributed control systems by leveraging Redis and containerization. The RA provides a unified, efficient interface between Redis based data streams and consumer systems. In the legacy architecture, digitized data flowed through the custom, UDP based Distributed Data Communication Protocol in the middle layer. In the current system, DDCP remains the ingestion path, while the RA serves as the decoupling layer. The proposed system replaces old VME digitizers with a SOM-based digitizer that communicates with Redis using the RA. The RA acts as both a performance-critical bridge and a protocol-agnostic adapter, ensuring compatibility with legacy control frameworks while enabling future scalability and modularity. This restructuring of the middle layer also helps the system achieve high throughput, reduce latency, and simplify the data path. Finally, we will demonstrate how RA is utilized in our two core products to deliver both legacy compatibility and future flexibility.

Joshi, S. [Fermilab]↗