Recent Progress in On-Focal-Plane ADC
Two 8 bit successive approximation analog-to-digital converters (ADC) and a 12 bit current mode incremental sigma delta ADC have been designed, fabricated, and tested.
analog-to-digital converters adc↗
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Hardness Assurance and Testing Techniques for High Resolution
Many different analog-to-digital converters (ADCs) have been.
analog-to-digital converters ADC hardness testing ↗
Progress in Voltage and Current Mode On-Chip Analog-to-Digital converters for CMOS Image Sensors
Two 8 bit successive approximation analog-to-digital converter (ADC) designs and a 12 bit current mode incremental sigma delta ADC have been designed, fabricated, and tested. The successive approximation test chip designs are compatible with active pixel sensor (APS) column parallel architectures with a 20.4 ??itch in a 1.2 ??-well CMOS process and a 40 ??itch in a 2 ??-well CMOS process. The successive approximation designs consume as little as 49 ??t a 500 KHz conversion rate meeting the low power requirements inherent in column parallel architectures. The current mode incremental sigma-delta ADC test chips designed to be multiplied among 8 columns in a semi-column parallel current mode APS architecture. The higher accuracy ADC consumes 800 ??t a 5 KHz.
analog-to-digital↗
Effect Of Clock Mode On Radiation Hardness Of An ADC
Report discusses techniques for testing and evaluating effects of total dosages of ionizing radiation on performances of high-resolution successive-approximation analog-to-digital converters (ADCs), without having to test each individual bit or transition. Reduces cost of testing by reducing tests to few critical parametric measurements, from which one determines approximate radiation failure levels providing good approximations of responses of converters for purpose of total-dose-radiation evaluations.
Lee, Choon I.↗
Analog-to-digital converter based on voltage-controlled superconducting devices
The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra-energy-efficient data conversion architectures that remain functional at deep cryogenic temperatures. Here, in this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a voltage-controlled quantum-enhanced Josephson junction field-effect transistor (JJFET). Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current-controlled superconducting devices while aligning naturally with CMOS-style design methodologies. Building on our previously developed Verilog-A compact model calibrated to experimental data, we design and simulate a three-bit JJFET-based flash ADC targeted for integration within cryogenic control and readout circuitry in quantum computing. The core comparator block is realized through careful bias current selection and augmented with a three-terminal nanocryotron to precisely define reference voltages. Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic-level restoration across stages. Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage-driven superconducting mixed-signal circuits. This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum–classical co-processors, low-power artificial intelligence accelerators, and next-generation energy-constrained computing platforms.
Analog-to-digital converter↗
Performance analysis of digital integrate-and-dump filters
Key design parameters associated with the operation of a digital integrate-and-dump filter are identified in this paper. Performance degradation effects associated with the selection of these parameters such as analog-to-digital converter (ADC) gain loading factor, number of bits used, predetection bandwidth, sampling rate, and accumulator length are considered. Numerical results of practical interest are also provided.
Chie, C. M.↗
Radiation-hard analog-to-digital converters for space and strategic applications
During the course of the Jet Propulsion Laboratory's program to study radiation-hardened analog-to-digital converters (ADCs), numerous milestones have been reached in manufacturers' awareness and technology development and transfer, as well as in user awareness of these developments. The testing of ADCs has also continued with twenty different ADCs from seven manufacturers, all tested for total radiation dose and three tested for neutron effects. Results from these tests are reported.
Gauthier, M. K.↗
Analog-To-Digital Converter For Sum-Of-Squares Measurements
Analog-to-digital converter (ADC) circuit designed as part of larger circuit intended to measure root-mean-square current on 20-kHz powerline. Provides digital output of 11 bits of data plus 1-bit overflow signal at sampling rate of 4 MHz. Output processed by multiplying-and-accumulating circuitry to obtain sum of squares and digitized current samples accumulated during preset number of consecutive sampling periods. Used to digitize current samples from ADC directly as alternative or auxiliary output. Notable features include low power and fast conversion.
Osborn, Stephen H.↗
Preliminary design and implementation of the baseline digital baseband architecture for advanced deep space transponders
The baseline design and implementation of the digital baseband architecture for advanced deep space transponders is investigated and identified. Trade studies on the selection of the number of bits for the analog-to-digital converter (ADC) and optimum sampling schemes are presented. In addition, the proposed optimum sampling scheme is analyzed in detail. Descriptions of possible implementations for the digital baseband (or digital front end) and digital phase-locked loop (DPLL) for carrier tracking are also described.
Nguyen, T. M.↗
Data collection in IMS: It's not as easy as it looks
Data collection in Ion Mobility Spectrometry (IMS) is not as easy an endeavor as it appears. Despite the advent of high speed personal computers and fast analog-to-digital converters (ADC's), care must be taken to ensure that reliable data are obtained in a timely fashion. This is especially true in hyphenated techniques, e.g. GC-IMS, where the amount of data increases dramatically when gas chromatography-ion mobility spectrometry (GC-IMS) data is being collected. Using the Graseby GC-IMS, with a gate repetition rate of 33 Hz, it is theoretically possible to collect 33 spectra per second. This collection rate is not realistically obtained due to a number of factors. Among these factors are inaccuracy of the timing signal from the IMS, the necessity to store the data, disk input/output limitations, disk operating system limitations, and program overhead. Taking these factors into account, we have achieved a data collection rate of 20 spectra per second. This paper will describe these problems, demonstrate the practical effects these problems present, and present methods for minimizing these effects.
Davis, Dennis M.↗
Resonant Tunneling Analog-To-Digital Converter
As sampling rates continue to increase, current analog-to-digital converter (ADC) device technologies will soon reach a practical resolution limit. This limit will most profoundly effect satellite and military systems used, for example, for electronic countermeasures, electronic and signal intelligence, and phased array radar. New device and circuit concepts will be essential for continued progress. We describe a novel, folded architecture ADC which could enable a technological discontinuity in ADC performance. The converter technology is based on the integration of multiple resonant tunneling diodes (RTD) and hetero-junction transistors on an indium phosphide substrate. The RTD consists of a layered semiconductor hetero-structure AlAs/InGaAs/AlAs(2/4/2 nm) clad on either side by heavily doped InGaAs contact layers. Compact quantizers based around the RTD offer a reduction in the number of components and a reduction in the input capacitance Because the component count and capacitance scale with the number of bits N, rather than by 2 (exp n) as in the flash ADC, speed can be significantly increased, A 4-bit 2-GSps quantizer circuit is under development to evaluate the performance potential. Circuit designs for ADC conversion with a resolution of 6-bits at 25GSps may be enabled by the resonant tunneling approach.
Broekaert, T. P. E.↗
Free-Flying Magnetometer Data System
The Free-Flying Magnetometer (FFM) is an autonomous "sensorcraft" developed at the Jet Propulsion Laboratory (JPL) for the Enstrophy sounding rocket mission. This mission was a collaborative project between the University of New Hampshire, Cornell University and JPL. The science goal of the mission was the study of current filamentation phenomena in the northern auroral region through multipoint measurements of magnetic field. The technical objective of the mission was the proof of concept of the JPL FFM design and the demonstration of an in-situ multipoint measurement technique employing many free-flying spacecraft. Four FFMs were successfully deployed from a sounding rocket launched from Poker Flats, Alaska on February 11, 1999. These hockey-puck-sized (80 mm diameter, 38 mm. height, 250 gram mass) free flyers each carry a miniature 3-axis flux-gate magnetometer that output +/- 2 V signals corresponding to a +/- 60,000 nT measurement range for each axis. The FFM uses a synchronized four-channel Sigma(Delta) Analog-to-Digital Converter (ADC) having a dynamic range of +/- 2.5V and converting at a rate of 279 samples/second/channel. Three channels are used to digitize the magnetometer signals to 17-bit (1.144 nT/bit) resolution. The fourth ADC channel is multiplexed for system monitoring of four temperature sensors and two battery voltages. The FFM also contains two sun sensors, a laser diode which emits a fan-shaped beam, a miniature S-band transmitter for direct communication to the ground station antennas, an ultra-stable Temperature Compensated Crystal Oscillator (TCXO) clock, an integrated data subsystem implemented in a Field-Programmable Gate Array (FPGA), a 4 Mbit Static Random Access Memory (SRAM) for data storage and Lithium Thionyl Chloride batteries for power. Communicating commands to the FFM prior to deployment is achieved with an infrared (IR) link. The FFM IR receiver responds to 9-bit pulse coded signals that are generated by an IR Light Emitting Diode (LED) in the payload for turning FFM power on or off and placing the FFM in a test mode or flight mode. The IR links are also used to synchronize (zero) the clocks onboard all the FFMs through a reset pulse originating from the payload GPS receiver that is issued when the FFMs are in flight mode. The FPGA based data subsystem manages continuous data collection from the four ADC channels and sun sensors, formatting and storing the data to SRAM, and controlling downlink transmission. The transmitter is powered only after a 2547 frame SRAM buffer has been filled (approx. 5 minutes of data). The data is Viterbi encoded and sent to the S-band transmitter via a First-In-First-Out (FIFO) buffer who's output is clocked at 100 bits/second. After the 26-second transmission, the transmitter is turned off to reduce noise coupling to the sensitive magnetometer. The data subsystem control consists of a master state machine that performs data flow management and is interfaced through a prioritized interrupt scheme to state machines that service the ADC, sun sensors and transmitter FIFO. Continuous data collection prevents the missing of data during transmission and provides implicit time tagging of the data acquired by the ADC because of synchronization with the TCXO clock.
Blaes, B.↗
Demonstration of 10 Kelvin Superconducting Electronics in an Infrared Imaging System
We report the successful operation of a superconducting niombium nitride (NbN) Josephson Junction-based analog-to-digital converter (ADC) in an infrared imaging system.
superconducting niobium nitride cryogenic componen↗
Preliminary Design and Implementation of the Baseline Digital Baseband Architecture for Advanced Deep Space Transponders
This article investigates and identifies the baseline design and implementation of the digital baseband architecture for advanced deep space transponders. Trade studies on the selection of the number of bits for the analog-to-digital converter (ADC) and optimum sampling schemes are presented. In addition, the proposed optimum sampling scheme is analyzed in detail. Descriptions of possible implementations for the digital baseband (or digital front end) and digital phase-locked loop (DPLL) for carrier tracking are also described.
Deep↗
Comparison of Total Dose Responses on High Resolution Analog-to-Digital Converter Technologies
This paper compares total dose effects on two different technology (CMOS and BiCMOS) 12-bit ADCs from the same manufacturer, Burr-Brown.
Dose Responses Analog-to-Digital Converter↗
Simple first order data compression processor concept
Data-compression processing systems based on an analog-to-digital converter /ADC/, includes a qualitative comparator for comparison of the ADC output with a ramp generator, which is connected as a bidirectional binary counter with selective inputs. A bidirectional ramp counter selects the proper ramp through a ramp generator selection network.
Anderson, T. O.↗
Integration of an Imaging System and A/D Converter System
The project is a camera demonstration system that has specific output modules. A high-speed amplifier interface will drive both a display and an analog-to-digital conveter (ADC) board.
Imaging System Camera↗
Captan+X Data Converter Integration
Fermi National Accelerator Laboratory's CAPTAN (Compact And Programmable daTa Acquisition Node) series provides a flexible hardware platform for data acquisition across a range of experiments and facilities. The latest iteration, CAPTAN+X, is built around a Kintex-7 FPGA supporting four FPGA Mezzanine Card (FMC) connections. As part of a broader laboratory effort to bring facility systems under a Model-Based Systems Engineering (MBSE) framework, CAPTAN+X is one of several systems slated to be incorporated into this modeling environment in the near term. A necessary step toward that goal is incorporating the platform's core functionality, which centers on integration with the LXD31K4 FMC, a data converter module combining dual AD9652 analog-to-digital converters and dual AD9142A digital-to-analog converters. Achieving compatibility required resolving pin-mapping conflicts between the LXD31K4's High Pin Count connector and the CAPTAN+X's available pin types, adapting a Board Support Project originally written for an UltraScale-class evaluation board to the Kintex-7 architecture, replacing incompatible primitives, restructuring clock distribution, and manually configuring chip initialization in place of an unsupported soft-processor-based approach. Functional verification of the ADC and DAC channels, followed by closed-loop testing combining both converters with real-time filtering, confirmed correct operation of the integrated system. These results establish a working hardware and firmware baseline for the CAPTAN+X platform, positioning it for future inclusion in the laboratory's growing MBSE modeling effort.
Espinoza, David [Illinois U., Urbana (main)]↗