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All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

BeyondPlanck: V. Minimal ADC Corrections for Planck LFI

We describe the correction procedure for Analog-to-Digital Converter (ADC) differential non-linearities (DNL) adopted in the Bayesian end-to-end BEYONDPLANCK analysis framework. This method is nearly identical to that developed for the official Planck Low Frequency Instrument (LFI) Data Processing Center (DPC) analysis, and relies on the binned rms noise profile of each detector data stream. However, rather than building the correction profile directly from the raw rms profile, we first fit a Gaussian to each significant ADC-induced rms decrement, and then derive the corresponding correction model from this smooth model. The main advantage of this approach is that only samples which are significantly affected by ADC DNLs are corrected, as opposed to the DPC approach in which the correction is applied to all samples, filtering out signals not associated with ADC DNLs. The new corrections are only applied to data for which there is a clear detection of the non-linearities, and for which they perform at least comparably with the DPC corrections. Out of a total of 88 LFI data streams (sky and reference load for each of the 44 detectors) we apply the new minimal ADC corrections in 25 cases, and maintain the DPC corrections in 8 cases. All these corrections are applied to 44 or 70 GHz channels, while, as in previous analyses, none of the 30 GHz ADCs show significant evidence of non-linearity. By comparing the BEYONDPLANCK and DPC ADC correction methods, we estimate that the residual ADC uncertainty is about two orders of magnitude below the total noise of both the 44 and 70 GHz channels, and their impact on current cosmological parameter estimation is small. However, we also show that non-idealities in the ADC corrections can generate sharp stripes in the final frequency maps, and these could be important for future joint analyses with the Planck High Frequency Instrument (HFI), Wilkinson Microwave Anisotropy Probe (WMAP), or other datasets. We therefore conclude that, although the existing corrections are adequate for LFI-based cosmological parameter analysis, further work on LFI ADC corrections is still warranted.

79 ASTRONOMY AND ASTROPHYSICS↗
DOE OSTI2026

Analog-to-digital converter based on voltage-controlled superconducting devices

The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra-energy-efficient data conversion architectures that remain functional at deep cryogenic temperatures. Here, in this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a voltage-controlled quantum-enhanced Josephson junction field-effect transistor (JJFET). Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current-controlled superconducting devices while aligning naturally with CMOS-style design methodologies. Building on our previously developed Verilog-A compact model calibrated to experimental data, we design and simulate a three-bit JJFET-based flash ADC targeted for integration within cryogenic control and readout circuitry in quantum computing. The core comparator block is realized through careful bias current selection and augmented with a three-terminal nanocryotron to precisely define reference voltages. Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic-level restoration across stages. Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage-driven superconducting mixed-signal circuits. This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum–classical co-processors, low-power artificial intelligence accelerators, and next-generation energy-constrained computing platforms.

Analog-to-digital converter↗
DOE OSTI2021

Quality assurance test of silicon photomultipliers and electronic boards for STAR event plane detector

The event plane detector (EPD), installed in the Solenoid Tracker at the Relativistic Heavy-Ion Collider located at the Brookhaven National Laboratory is a plastic scintillator-based device that measures the reaction centrality and event plane in the forward region of the relativistic heavy-ion collisions. We used silicon photomultiplier (SiPM) arrays to detect the photons produced in the scintillator via the fiber connection. Signals from the SiPM arrays were amplified by the front-end electronic (FEE) board, and sent to the analog-to-digital converter (ADC) boards for further processing via the receiver (RX) board. The full EPD system consisted of 24 super-sectors (SSs); each SS was equipped with two SiPM boards, two FEE boards and two RX boards, and they corresponded to 744 readout channels. All these boards were mass produced at the University of Science and Technology of China, with a dedicated quality assurance (QA) procedures applied to identify any problems before deployment. This article describes the details of the QA method and the related test system. As a result, the QA test results are presented along with the discussions.

EPD↗
DOE OSTI2024

Miniaturized Magnetoelastic Sensor System

This article describes the design, assembly, and implementation of a hand-held, magnetic-field-based sensor system that can be adapted for a variety of sensing applications. The miniaturized system is based on Chemical Identification by Magneto-Elastic Sensing (ChIMES) technology, which uses three concentric solenoid coils to wirelessly interrogate a sensor body comprised of a response material coupled to a magnetoelastic wire. The response material expands when it encounters a target, imposing mechanical stress on the wire and altering its magnetic permeability. The sensor bodies are passive, requiring no external power source, and they are small, measuring about 15 mm in length and 3.0 mm in diameter. Up to four sensor bodies can be configured as an evenly-spaced linear array. The sensor system operates by applying a low-frequency, current-stabilized, filtered triangle wave to a uniform-density excitation coil to switch the magnetic domains within the wire. Further, the responses from the sensors are picked up by a detection coil as stress-induced changes in the Faraday voltage, and the strong magnetic field induced by the excitation coil in the detection coil is nullified by a cancellation coil reverse-wound in series with the detection coil. The responses of the sensors in an array are separated in time by a linear gradient dc biasing coil. The sensors can be interrogated through metallic and nonmetallic barriers. The signals from the detection coil and the excitation coil are digitized by a pair of bipolar analog-to-digital converters (ADCs). A Raspberry Pi single-board computer (SBC) and associated software perform data acquisition and control all aspects of the sensor system hardware. The program allows the user to select the number of sensors in the array, the type of signal that is being collected, and the number of samples to take. The program also allows for signal processing of the sensor data, such as baseline correction. The program can differentiate sensor peaks from each other and calculate the magnitude of each sensor response with less than 1% error. The data are then displayed along with a graph of the signal.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

A 24-Channel Digitizer With a JESD204B-Compliant Serial Interface for High-Speed Detectors

In this report a 24-channel application-specific integrated circuit (ASIC) for the readout of high-speed CMOS active pixel sensors for charged particle detection is presented. The chip comprises 24 preamplifiers, 24 distinct 12-bit, 25 MSPS Pipelined analog-to-digital converters (ADCs) with self-calibration, an internal phase-locked loop (PLL), and a 3 Gbps serial interface that conforms to the JESD204B standard. To simplify interfacing with a variety of sensors, the ASIC also includes an automatic offset calibration loop. The high level of integration of the ASIC reduces overall system cost and area, and exploiting the signal characteristics of the image sensor allows the ADC to be optimized for reduced power dissipation. The use of an integrated serializer and an industry standard protocol simplifies integration of the ASIC into a complete camera system. The ASIC, called the High-Speed Image Preprocessor Targeted for Electron Readout, or HIPSTER, with a die area of 64.26 mm 2 , is packaged in a 480-ball grid array (BGA) and is fabricated in 180-nm CMOS technology. HIPSTER achieves typical differential nonlinearity (DNL) < 0.55 LSB, input-referred thermal noise of $114.5 μV-rms, and a bit error rate (BER) of better than 10-14. The power dissipation is 98 mW/channel.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

Switch leakage mitigation through differential cancellation

High speed analog-to-digital converters (ADC), switched-capacitor delay elements, and pulsed radio frequency (RF) systems all require switches in the signal path operating at high switching speeds, providing low resistance when enabled, and providing high signal isolation when disabled. In semiconductor technologies such as CMOS, the enabled state resistance directly scales with the sizing of the switch device, where a larger width switch provides a lower enabled state resistance. As the device width is increased, so is the capacitance formed between the gate, drain, and source of the device.

42 ENGINEERING↗
DOE OSTI2024

All-digital Sensor System for Distributed Downhole Pressure Monitoring in Unconventional Fields

This project developed and validated (through field tests) a new low-cost all-digital pressure sensing technology for in situ distributed downhole pressure monitoring in unconventional oil and gas (UOG) fields. The all-digital sensing technology uses a built-in non-electric analog-to-digital converter (ADC) to transform the pressure information into a combination of binary (ON/OFF) states. As such, the system does not need downhole electronics for signal conditioning and telemetry. The all-digital sensors can be remotely logged over a long distance, and many sensors can be multiplexed for distributed sensing. Based on a review of unconventional wells in the Lower 48 states, the specification of the sensor is to measure pressure up to 69 MPa (10,000 psi) and temperature up to 250°C. A sensor with a helical bourdon sensing element and a digital signal decoder of 50 mm diameter and 109 mm length was constructed. The helical bourdon sensing element was made of 304L stainless steel and filled with motor oil. The digital converter was made up of 8 digital reading pads constructed of high-temperature epoxy with conductive inserts made of stainless steel. The sensor had a linear response to pressure with an accuracy of 0.14 MPa (20 psi). To withstand the high pressure, the sensor was enclosed in a stainless-steel pressure housing with a wall thickness of 5.5 mm, a diameter of 73 mm, and a length of 724 mm. In the laboratory tests, the sensor exhibited no temperature-related effects on the results. The sensor did not show drift over a 14-day test period at elevated pressure. A field test was conducted where the sensor was deployed in a test wellbore at the Quest drilling test facility to a depth of 0 feet over three weeks. The sensor was attached to the production rods, along with a downhole reference sensor of PPS27 type, which is a permanent downhole monitoring system. During the testing phase, the test well annular blow-out preventer was closed, and the well was pressurized at the surface to 11 MPa (1600 psi). The sensor read the elevated bottom hole pressure of 1500 psi. A multiplexing unit was created for the sensor to deploy multiple sensors on one data transmission line in a distributed approach. The multiplexing unit was tested in a simulated environment of 3048 m (10,000 ft) with five sensors distributed. The sensors were pressurized at different intervals. The multiplexed sensors recorded the correct pressure, and the multiplexing did not interfere with the readings. The proposed concept of an all-digital pressure sensor for harsh downhole environments was designed, manufactured, and tested in the laboratory and tested at the field to a up to 69 MPa and 250°C. This technology has high-temperature tolerance and has potential in downhole areas outside oil and gas, such as carbon capture and storage (CCS) and geothermal wells. The sensor concept has been proven in this project, but to create a commercially viable product, manufacturing a sensor with a smaller diameter needs to be performed.

02 PETROLEUM↗
DOE OSTI2022

Multiplexed Readout for an Experiment with a Large Number of Channels Using Single-Electron Sensitivity Skipper-CCDs

This paper presents the implementation of a multiplexed analog readout electronics system that can achieve single-electron counting using Skipper-CCDs with non-destructive readout. The proposed system allows the best performance of the sensors to be maintained, with sub-electron noise-level operation, while maintaining low-bandwidth data transfer, a minimum number of analog-to-digital converters (ADC) and low disk storage requirement with zero added multiplexing time, even for the simultaneous operation of thousands of channels. These features are possible with a combination of analog charge pile-up, sample and hold circuits and analog multiplexing. The implementation also aims to use the minimum number of components in circuits to keep compatibility with high-channel-density experiments using Skipper-CCDs for low-threshold particle detection applications. Performance details and experimental results using a sensor with 16 output stages are presented along with a review of the circuit design considerations.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

High power handling digitizer using photonics

Devices, methods for analog-to-digital converters (ADCs) that perform high-dynamic range measurements based on optical techniques are disclosed. In one example aspect, an optical encoder includes a polarization rotator configured to receive a train of optical pulses, and an electro-optic (EO) modulator coupled to an output of the polarization rotator. The EO modulator is configured to receive a radio frequency (RF) signal and to produce a phase modulated signal in accordance with the RF signal. The optical encoder also includes a polarizing beam splitter coupled to the output of the EO modulator; and an optical hybrid configured to receive two optical signals from the polarizing beam splitter and to produce four optical outputs that are each phase shifted with respect to one another.

DeVore, Peter Thomas Setsuda↗
DOE OSTI2021

Hardware intrusion detection system

An apparatus for intrusion detection includes processing circuitry, a switch, signal detection circuitry, and an analog-to-digital converter (“ADC”). The processing circuitry is coupled to send a challenge signal to a device when the device is coupled to the processing circuitry. The switch is coupled to be enabled and disabled by the processing circuitry. The switch is for coupling to the device to receive a response signal in response to the challenge signal sent by the processing circuitry. The signal detection circuitry is coupled to receive the response signal in via the switch, when the processing circuitry enables the switch. The ADC is coupled to take measurements of the signal detection circuitry at a first output. The processing circuitry is coupled to the ADC and configured to analyze whether an intruder is present in the device based on the measurements of the signal detection circuitry.

Edwards, Nathan J.↗
DOE OSTI2022

Multi-channel high-speed converter clock synchronization with autonomous coherent deterministic latency

A system and corresponding method that achieves coherency and deterministic latency (CDL) autonomously upon power on is disclosed. The system, for example, a multi-channel RF system, may require CDL with respect to the digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) assigned to the channels in the system. CDL is achieved through a timed combination of external reference and synchronization signals, resetting and disabling of various clock dividers, and enabling clock generation. In addition to synchronizing all of the clocks, the data acquisition sequence must be synchronized across all of the channels, whether they are on chips, cards, or chassis. Data acquisition synchronization may be implemented using an initiator/target or a wired OR mode configuration.

Brady, Charles E.↗
DOE OSTI2024

High power handling digitizer using photonics

Devices, methods for analog-to-digital converters (ADCs) that perform high-dynamic range measurements based on optical techniques are disclosed. In one example aspect, an optical encoder includes a polarization rotator configured to receive a train of optical pulses, and an electro-optic (EO) modulator coupled to an output of the polarization rotator. The EO modulator is configured to receive a radio frequency (RF) signal and to produce a phase modulated signal in accordance with the RF signal. The optical encoder also includes a polarizing beam splitter coupled to the output of the EO modulator; and an optical hybrid configured to receive two optical signals from the polarizing beam splitter and to produce four optical outputs that are each phase shifted with respect to one another.

DeVore, Peter Thomas Setsuda↗
DOE OSTI2024

Jamming Detection for Low-Resolution SC-FDE Systems: A Machine Learning Approach

Jammers interfere with communication between base stations (BSs) and legitimate users, leading to degradation of wireless system performance. Our study focuses on jamming detection for wideband single-carrier frequency domain equalization (SC-FDE) systems with low-resolution analog-to digital converters (ADCs). In such systems, jamming detection is challenging because traditional analytical approaches cannot be directly applied due to the delay dispersion in wideband channels and the non-linearity induced by low-resolution ADCs. We propose a machine learning (ML)-based jamming detection method that directly uses the quantized receive signals. Significantly, our ML-based detector can be integrated into existing standard frameworks, such as unique word (UW)-based SC-FDE systems, as it uses existing pilots without requiring additional pilots for jamming detection. Through numerical simulations, we show that two or more bits provide satisfactory performance compared to unquantized scenarios. Additionally, we demonstrate that using more and well-separated pilot symbols improves performance.

99 GENERAL AND MISCELLANEOUS↗
DOE OSTI2024

The SparkPix-S ASIC for the sparsified readout of 1 MHz frame-rate X-ray cameras at LCLS-II: pixel design and simulation results

Exploiting the “sparse” nature of the information in XPCS (X-ray Photon Correlation Spectroscopy) and XSVS (Speckle Visibility Spectroscopy) experiments, we present the SparkPix-S, a 3-sides buttable Application Specific Integrated Circuit (ASIC) based on a sparsified readout strategy for large-format hybrid detectors. The SparkPix-S architecture, based on the successful ePix family, will be composed as follows: a front-end 2-D matrix of 384×352 square pixels with 50 µm pitch is arranged to match the dimensions of a PIN Si-sensor matrix; charge readout, signal shaping and amplitude discrimination is performed at pixel-level, by means of a low-power (<18 µW) analog processor, which, in case of an event, negotiates access to an analog bus placed every other column; on the chip periphery (balcony), the information on each bus is digitized by an array of successive approximation analog-to-digital converters (SAR-ADCs) running at 10 Msps; on the digital back-end the global logic will generate the output data stream using low-voltage differential signalling (LVDS). A first prototype of the SparkPix-S, with a reduced matrix size of 96×96 pixels, is currently under production on a 130 nm CMOS technology. Simulated performance results show an equivalent noise charge <60 el. r.m.s. at 1 MHz repetition rate, with a maximum input energy of 60 keV and capability to discriminate charge signals with equivalent energy as low as 900 eV.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

Physical Layer Security at a Point-to-Point MIMO System With 1-Bit DACs and ADCs

Low-resolution converters reduce the power consumption of wireless devices and help enable large energy-efficient arrays. In this letter, we evaluate the secrecy rate for the extreme case of 1-bit single-user multiple-input multiple-output systems following two signaling approaches. In the first method, the system uses discrete signaling. In the second, the system combines Gaussian signaling with artificial noise alongside power allocation. In the first case, we give a closed-form expression of the secrecy rate and propose an algorithm that provides near-optimal results for low signal-to-noise ratios (SNRs). Further, in the second scenario, depending on the channel state information, we suggest different precoding plans and derive a secrecy rate lower bound. At low SNR, power is allocated to the main signal. Only at high SNR is optimal power allocation effective. Moreover, knowing the eavesdropper channel greatly improves the system’s secrecy.

1-bit digital-to-analog (DAC) and analog-to-digita↗
DOE OSTI2021

Characterization and QC practice of 16-channel ADC ASIC at cryogenic temperature for Liquid Argon TPC front-end readout electronics system in DUNE experiment

ColdADC is a low-noise 16-channel analog-to-digital converter ASIC designed for cold readout electronics of Liquid Argon Time Projection Chambers (LArTPCs) in the Deep Underground Neutrino Experiment (DUNE). ColdADC was specifically designed for operation at cryogenic temperatures (77 K–89 K). Cold electronics is considered to be an enabling technology for liquid argon detectors in neutrino experiments. The main function of the chip is to digitize signals from the 16-channel charge-sensitive amplifier designed at BNL (LArASIC) and send digitized signals to the data aggregator and serializer chip (COLDATA). ColdADC operates with a resolution of 12 bits and a sampling rate of 2 MS/s per channel. A complete characterization of prototype chips was conducted at cryogenic temperature, involving power consumption, noise and linearity performance. In the first DUNE Far-Detector module, 384000 data channels will be read out, corresponding to 24000 ColdADC chips. Therefore, systematic testing of ColdADC chips at cryogenic temperature is vital for the quality and reliability of DUNE Single-Phase modules. We have developed a Quality Control (QC) test stand that includes ColdADC evaluation and characterization at cryogenic temperature. The QC procedure was applied to a first batch of 33 chips, corresponding to 528 data channels. The obtained results meet all the required DUNE specifications for ColdADC. Moreover, the testing outcome allowed us to identify possibilities of performance optimization that are currently being addressed in the design of the next version of the chip. The Quality Control procedure is proved to be successful and will be a reference design for future large-batch production testing of final ColdADC ASICs.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

Improving Signal to Noise Ratios in Ion Mobility Spectrometry and Structures for Lossless Ion Manipulations (SLIM) using a High Dynamic Range Analog-to-Digital Converter

Signal digitization is a commonly overlooked part of ion mobility-mass spectrometry (IMS-MS) workflows, yet it is a significant contributor for determining signal-to-noise ratios and MS resolution. Here we report on the integration of a 2 GS/s, 14-bit ADC with a structures for lossless ion manipulations (SLIM)-IMS-MS and compare the performance to a commonly used 8-bit ADC. The 14-bit ADC provided an effective reduction in digitized noise by factor of ~6, owing largely to the use of smaller bit sizes. The low baseline allowed the threshold voltage levels to be set very close to the MCP baseline voltage, allowing for as much signal to be acquired as possible without causing overloading or excessive digitization of MCP baseline noise. Analyses of Agilent tuning mixture ions and a complex mixture of heavy labeled phosphopeptides showed that the 14-bit ADC (compared to the 8-bit ADC) provided a modest signal-to-noise increase (~1.5 to 2-fold) for high intensity ions, such as the Agilent tuning mixture ions and the 2+ and 3+ charge states of many phosphopeptide constituents. However, signal enhancements were as much as 10-fold for low intensity ions, and the 14-bit ADC enabled discernable signal intensities otherwise lost using an 8-bit digitizer. Additionally, the 14-bit ADC required ~14-fold fewer mass spectra to be averaged to produce a mass spectrum with similar S/N as the 8-bit ADC under identical conditions, potentially providing an order of magnitude higher measurement throughput. The high resolution, low baseline, and fast speed of the new 14-bit ADC enables high performance digitization of MS, IMS-MS, and SLIM-IMS-MS spectra, and allows a much fuller picture of analyte profiles in complex mixtures to be acquired.

data acquisition, digitization, ion mobility spect↗